HI-3582 HOLTIC [Holt Integrated Circuits], HI-3582 Datasheet - Page 4

• Manufacturer Part Number: HI-3582
• Description: 3.3V ARINC 429 TERMINAL IC
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL DESCRIPTION (cont.)
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
ARINC 429 DATA FORMAT
Control register bit CR15 is used to control how individual bits in the
received or transmitted ARINC word are mapped to the HI-3582/
HI-3583 data bus during data read or write operations. The
following table describes this mapping:
CR15=0
CR15=1
CR15=0
CR15=1
ARINC
ARINC
ARINC
ARINC
DATA
DATA
RIN1A
RIN2A
RIN1B
RIN2B
BUS
BUS
BIT
BIT
BIT
BIT
OR
OR
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
13 12 11 10
16 15 14 13 12 11 10
STATE
ZERO
NULL
ONE
v
v
DD
DD
FIGURE 1. ARINC RECEIVER INPUT
GND
GND
9
DIFFERENTIAL VOLTAGE
31 30 32
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
BYTE 2
BYTE 1
9
DIFFERENTIAL
AMPLIFIERS
1
8
2
7
3
6
HOLT INTEGRATED CIRCUITS
COMPARATORS
4
5
5
4
HI-3582, HI-3583
6
3
7
2
NULL
ONES
ZEROES
8
1
4
The HI-3582/HI-3583 guarantee recognition of these levels with a
common mode Voltage with respect to GND less than ±4V for the
worst case condition (3.0V supply and 13V signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
RECEIVER LOGIC OPERATION
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
The ARINC 429 specification contains the following timing specifi-
cation for the received data:
The HI-3582/HI-3583 accept signals that meet these specifica-
tions and rejects signals outside the tolerances. The way the logic
operation achieves this is described below:
PULSE FALL TIME
PULSE RISE TIME
1. Key to the performance of the timing checking logic is an
accurate 1MHz clock source. Less than 0.1% error is recom-
mended.
2. The sampling shift registers are 10 bits long and must
show three consecutive Ones, Zeros or Nulls to be consid-
ered valid data. Additionally, for data bits, the One or Zero in
the upper bits of the sampling shift registers must be followed
by a Null in the lower bits within the data bit time. For a Null in
the word gap, three consecutive Nulls must be found in both
the upper and lower bits of the sampling shift register. In this
manner the minimum pulse width is guaranteed.
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
4. The Word Gap timer samples the Null shift register every
PULSE WIDTH
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter
is incremented. A count of 3 will enable the next reception.
DATA BIT RATE MAX
DATA BIT RATE MIN
BIT RATE
100K BPS ± 1% 12K -14.5K BPS
HIGH SPEED
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
HIGH SPEED
125K BPS
83K BPS
34.5 to 41.7 µsec
LOW SPEED
10 ± 5 µsec
10 ± 5 µsec
LOW SPEED
10.4K BPS
15.6K BPS