HI-3582 HOLTIC [Holt Integrated Circuits], HI-3582 Datasheet - Page 5

• Manufacturer Part Number: HI-3582
• Description: 3.3V ARINC 429 TERMINAL IC
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The receiver parity circuit counts Ones received, including the
parity bit. If the result is odd, then a "0" will appear in the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO. ARINC words which do not
meet the necessary 9th and 10th ARINC bit or label matching are
ignored and are not loaded into the receive FIFO. The following
table describes this operation.
CONTROL
BIT
SEL
EN
D/R
HF
FF
ZEROS
ONES
NULL
CONTRO
CONTROL
LOAD
MUX
FIFO
EOS
MEMORY
L
LABEL
16 x 8
SHIFT REGISTER
SHIFT REGISTER
SHIFT REGISTER
/
COMPARE
DECODE
LABEL /
FIGURE 2.
32 BIT SHIFT REGISTER
32 TO 16 DRIVER
HOLT INTEGRATED CIRCUITS
32 X 32
TO PINS
FIFO
HI-3582, HI-3583
RECEIVER BLOCK DIAGRAM
WORD GAP
5
BIT CLOCK
CR2(3) ARINC word CR6(9) ARINC word
DATA
CONTROL
START
0
1
1
0
0
1
1
1
1
CONTROLBITS
R/W
CR0, CR14
PARITY
CHECK
WORD GAP
SEQUENCE
DETECTION
matches
CONTROL
ERROR
TIMER
label
Yes
Yes
Yes
CONTROL
No
No
No
X
X
X
BITS
32ND
BIT
END
ERROR
CLOCK
SEQUENCE
BIT CLOCK
COUNTER
END OF
0
0
0
1
1
1
1
1
1
OPTION
CLOCK
AND
BIT
CR7,8 (10,11)
bits 9,10
match
Yes
Yes
Yes
No
No
No
X
X
X
CLOCK
Ignore data
Ignore data
Ignore data
Ignore data
Ignore data
Load FIFO
Load FIFO
Load FIFO
Load FIFO
CLK
FIFO