HI-3597 HOLTIC [Holt Integrated Circuits], HI-3597 Datasheet - Page 5

• Manufacturer Part Number: HI-3597
• Description: Octal ARINC 429 Receivers with Label Recognition and SPI Interface
• Manufacturer: HOLTIC [Holt Integrated Circuits]

FUNCTIONAL DESCRIPTION
Control Word Register
Each HI-359x receive channel is assigned a 16-bit
Control Register which confi gures that receiver. Con-
trol Register bits CR15 - CR0 are loaded from a 16-bit
data value appended to SPI instruction n4 hex, where
“n” is the channel number 1-8 hex. Writing to the Con-
trol Register also clears the data FIFO for that channel.
The Control Register contents may be read using SPI
instruction n5 hex. Table 3 summarizes the Control Reg-
ister bits functions.
CR Bit
(MSB)
(LSB)
CR10
CR15
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
to
Table 3. Control Register Bits Functions
Parity Check
Recognition
(Loopback)
Function
Data Rate
Defi nition
Not Used
Receiver
Receiver
Receiver
Self-Test
Receiver
Label Bit
Decoder
RFLAG
Enable
Enable
ARINC
Select
Reset
Order
Label
-
-
State
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-
-
Description
Data rate = ACLK/10 (ARINC 429
High-Speed)
Data rate = ACLK/80 (ARINC 429
Low-Speed)
FLAG goes high when receive FIFO is
not empty (Contains at least one word)
FLAG goes high when receive FIFO
is full
Label recognition disabled
Label recognition enabled
Normal Operation
Reset this receiver (Clear receiver
logic and FIFO). The receive channel
is disabled if CR3 is left high
Receiver parity check disabled
Receiver odd parity check enabled
Receiver’s inputs are connected to the
Transmit Register serial data output.
Normal operation
Receiver Decoder Disabled
ARINC bits 10 and 9 must match CR7
and CR8
If receiver decoder is enabled, the
ARINC bit 10 must match this bit
If receiver decoder is enabled, the
ARINC bit 9 must match this bit
Label bit order reversed (See Table 5)
Label bit order same as received (See
Table 5)
Control register read returns “0” for
these bits
HI-3596, HI-3597, HI-3598, HI-3599
HOLT INTEGRATED CIRCUITS
5
Status Register
The HI-359x devices have a single 16-bit Status Reg-
ister which is read to determine status for the eight
received data FIFOs. The Status Register is read using
SPI instruction n6 hex. Table 4 summarizes the Status
Register bits functions.
CR Bit
(MSB)
(LSB)
SR10
SR14
SR15
SR0
SR1
SR2
SR6
SR7
SR8
SR9
to
to
Table 4. Status Register Bits Functions
FIFO Empty
FIFO Empty
FIFO Empty
FIFO Empty
Function
Receiver 1
Receiver 2
Receiver 3
Receiver 7
Receiver 8
Receiver 1
Receiver 2
Receiver 3
Receiver 7
Receiver 8
FIFO Full
FIFO Full
FIFO Full
FIFO Full
to
to
State
0
1
0
1
0
1
0
1
0
1
0
1
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Description
Receiver 1 FIFO contains valid data.
Resets to Zero when all data has been
read. FLAG pin refl ects the state of
this bit when CR1=”0”
Receiver 1 FIFO is empty
Receiver 2 FIFO contains valid data.
Receiver 2 FIFO is empty
Receiver 8 FIFO contains valid data.
Receiver 8 FIFO is empty
Receiver 1 FIFO not full. FLAG pin
refl ects the state of this bit when
CR1=”1”
Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within one
ARINC word period.
Receiver 2 FIFO not full.
Receiver 2 FIFO full.
Receiver 8 FIFO not full.
Receiver 8 FIFO full.
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