HI-3597 HOLTIC [Holt Integrated Circuits], HI-3597 Datasheet - Page 9

• Manufacturer Part Number: HI-3597
• Description: Octal ARINC 429 Receivers with Label Recognition and SPI Interface
• Manufacturer: HOLTIC [Holt Integrated Circuits]

compared to the fi rst (MSB) bit of each SPI 8-bit data
fi eld from SPI instruction n1 hex, where “n” is the chan-
nel number 1-8 hex.
If a channel Control Register CR2 bit equals ”0,” the cor-
responding receiver recognizes all label values as valid,
as shown in Table 9.
Reading the Label Memory
The contents of each channel’s Label Memory may be
read via the SPI interface using instruction n2 hex where
“n” equals the channel number 1-8 hex, as described in
Table 2.
Digital Transmit Function
The Transmit Register can be used as a digital transmit-
ter by connecting the TX1 and TX0 pins to an external
ARINC 429 line driver such as the HI-8570 or HI-8571
(except HI-3599).
Loopback Self-Test
The HI-359x devices may use the Transmit Register
to execute user-defi ned self-test sequences (loopback
test) for each receiver. This feature may be individually
enabled for each receiver by resetting Control Register
CR5 bit to “0”. A 32-bit test word is loaded to the Trans-
mit Register using SPI instructions n8 hex (for ARINC
429 high-speed data rate) or n9 hex (for ARINC 429 low
speed). Upon completion of the instruction, the word is
shifted out of the register and routed to all receivers.
If self-test mode is enabled and the receive channel
is set to the correct speed, each channel will receive
the test word as if it came from an external ARINC 429
bus. If loopback is not enabled, the channel ignores the
self-test word and continues to respond to the external
ARINC 429 bus (Note: In the case of HI-3597, RIN1A
and RIN1B pins are not available). In all cases, the serial
test word may be observed at the TX1 and TX0 pins
(except HI-3599), as shown in Table 10.
NOTE: The fi rst bit shifted into the Self Test register will
be the fi rst bit sent to the receivers and the TX1 and TX0
pins. In ARINC 429 protocol, this bit is the LSB.
TX1
0
1
0
Table 10. Test Outputs
TX0
0
0
1
ARINC 429 State
HI-3596, HI-3597, HI-3598, HI-3599
ZERO
NULL
ONE
HOLT INTEGRATED CIRCUITS
9
Line Receiver Input Pins
The HI-3598 has two sets of Line Receiver input pins,
RINA/B and RINA/B-40. Only one pair may be used
to connect to the ARINC 429 bus. THE RINA/B pins
may be connected directly to the ARINC 429 bus. The
RINA/B-40 pins require an external 40KΩ resistor to be
added in series with each ARINC input without affect-
ing the ARINC input thresholds. This option is especially
useful in applications where lightning protection circuitry
is also required.
When using the RINA/B-40 pins, each side of the ARINC
bus must be connected through a 40KΩ series resistor
in order for the chip to detect the correct ARINC levels.
The typical 10V differential signal is translated and input
to a window comparator and latch. The comparator lev-
els are set so that with the external 40KΩ resistors, they
are just below the standard 6.5V minimum ARINC data
threshold and just above the standard 2.5V maximum
ARINC null threshold.
When using HI-3596, HI-3597 or HI-3599, only one set
of ARINC 429 receive inputs are provided for each chan-
nel. The standard HI-3596, HI-3597 and HI-3599 use the
direct-connection RINA / RINB pins. The HI-3596-40,
HI-3597-40 and HI-3599-40 devices use the RINA-40 /
RINB-40 pins and require external 40KΩ series resis-
tors. See the Ordering Information table for complete
part number options.
Please refer to the Holt AN-300 Application Note for
additional information and recommendations on light-
ning protection of Holt line drivers and line receivers.
Master Reset (MR)
Assertion of Master Reset (MR) causes immediate ter-
mination of data reception. The eight Receive FIFOs
are cleared. Status Register FIFO fl ags and FIFO status
output signals are also cleared. Master Reset does not
affect the eight channel Control Registers. Master Reset
may be asserted using the MR input pin (HI-3596 and
HI-3598 only) or by executing SPI instruction n7 hex.
An individual receive channel can be reset by setting
its corresponding Control Register CR3 bit to “1”. This
clears the channel’s receiver logic and Receive FIFO
and disables the receiver until CR3 is reset to “0”. For
applications requiring less than eight channels, unused
receivers should be held in reset by setting the corre-
sponding Control Register CR3 bits.