SSD1805TR1 ETC2 [List of Unclassifed Manufacturers], SSD1805TR1 Datasheet - Page 12

• Manufacturer Part Number: SSD1805TR1
• Description: 132 x 68 STN LCD Segment / Common Monochrome Driver with Controller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

6.11 V
This pin is the system power supply pin of bus IO buffer. Please refer to figure 19 on page 48 for connection
example.
6.12 V
This pin is the system power supply pin of the logic block.
6.13 V
Reference voltage input for internal DC-DC converter. The voltage of generated V
factor (2X, 3X, 4X or 5X) times V
Note: Voltage at this input pin must be larger than or equal to V
6.14 V
The V
6.15 V
Reference voltage input for internal DC-DC converter. The voltage of generated V
factor (2X, 3X, 4X or 5X) times V
Note: Voltage at this input pin must be equal to V
6.16 V
This pin is the ground of internal operation amplifier. In normal power mode, it must connect to V
power mode, it must connect to V
6.17 V
This pin is the power supply pin of the internal operation amplifier. It must connect to V
6.18 V
This is the most positive voltage supply pin of the chip. It can be supplied externally or generated by the
internal DC-DC converter. If the internal DC-DC converter generates the voltage level at V
level is used for internal referencing only. The voltage level at V
circuitry.
6.19 V
This is an input pin to provide an external voltage reference for the internal voltage regulator. The function of
this pin is only enabled for the External Input chip models which are required special ordering. For normal
chip model, please leave this pin NC (No connection).
6.20 V
This pin is the input of the built-in voltage regulator for generating V
selected (IRS pulled low) to generate the LCD driving level, V
connected between V
6.21 M/
This pin is the master/slave mode selection input. When this pin is pulled high, master mode is selected,
which CL, M, MSTAT and /DOF signals will be output for slave devices. When this pin is pulled low, slave
mode is selected, which CL, M, /DOF are required to be input from master device. MSTAT will still be an
output signal in slave mode.
6.22 CLS
This pin is the internal clock enable pin. When this pin is pulled high, internal clock is enabled. The internal
clock will be disabled when it is pulled low, an external clock source must be input to CL pin for normal opera-
tion.
Solomon Systech
SS
CI
SS
SS1
LREF
HREF
FS
is the ground reference of the system.
DDIO
DD
OUT
F
S
SS
and V
F
, and V
CI
CI
CI
with respect to V
with respect to V
. Please refer to figure 19 on page 48 for the detail.
F
and V
OUT
, respectively (see application circuit diagrams).
SS
.
SS1
SS1
.
.
OUT
DD
, two external resistors, R
.
OUT
Jun 2004 P 12/52
OUT
pin is not used for driving external
. When external resistor network is
OUT
OUT
OUT
Rev 1.1
equals to the multiple
equals to the multiple
.
1
and R
OUT
SSD1805 Series
, the voltage
2
, should be
SS
. In low