SSD1805TR1 ETC2 [List of Unclassifed Manufacturers], SSD1805TR1 Datasheet - Page 28

• Manufacturer Part Number: SSD1805TR1
• Description: 132 x 68 STN LCD Segment / Common Monochrome Driver with Controller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

9
9.1
To read data from the GDDRAM, input High to
input Low to
interface mode. In normal data read mode, GDDRAM column address pointer will be increased by one
automatically after each data read. However, no automatic increase will be performed in read-modify-write
mode. Also, a dummy read is required before first valid data is read. See Figure 3 on page 15 in Functional
Block Descriptions section for detail waveform diagram. To write data to the GDDRAM, input Low to
R/W ( WR )
mode, it is always in write mode. GDDRAM column address pointer will be increased by one automatically
after each data write. It should be noted that, after the automatic column address increment, the pointer will
NOT wrap round to 0. The pointer will exit the memory address space after accessing the last column.
Therefore, the pointer should be re-initialized when progress to another page address.
D/ C
0
0
1
1
9.2
This command specifies the lower nibble of the 8-bit column address of the display data RAM. The column
address will be increased by each data access after it is pre-set by the MCU.
9.3
This command specifies the higher nibble of the 8-bit column address of the display data RAM. The column
address will be increased by each data access after it is pre-set by the MCU.
9.4
This command is to enable any one of the eight internal resistor sets for different gains when using internal
resistor network (IRS pin pulled high). In other words, this command is used to select which contrast curve
from the eight possible selections. Please refer to Functional Block Descriptions section for detail calculation
of the LCD driving voltage.
9.5
This command turns on/off the various power circuits associated with the chip. There are two related power
sub-circuits could be turned on/off by this command. Internal voltage booster is used to generate the positive
voltage supply (V
option is turned off. Output op-amp buffer is the internal divider for dividing the different voltage levels from
the internal voltage booster, V
off.
9.6
This command is to set Display Start Line register to determine starting address of display RAM to be
displayed by selecting a value from 0 to 67. With value equals to 0, D0 of Page 0 is mapped to COM0. With
value equals to 1, D1 of Page0 is mapped to COM0 and so on. Display start line values of 0 to 67 are
assigned to Page 0 to 8. Please refer to Table 5 on Page 17 as an example for display start line set to 24
(18h).
Solomon Systech
COMMAND DESCRIPTIONS
Data Read / Write
Set Lower Column Address
Set Higher Column Address
Set Internal Gain Resistors Ratio
Set Power Control Register
Set Display Start Line
pin and High to
E( RD )
R/W ( WR )
0
1
0
1
OUT
pin and High to
) from the voltage input (V
D/ C
OUT
pin for both 6800-series and 8080-series parallel mode. For serial interface
. External voltage sources should be fed into this driver if this circuit is turned
Table 11 - Automatic Address Increment
D/ C
pin for 8080-series parallel mode. No data read is provided in serial
Action
Write Command
Read Status
Write Data
Read Data
CI
- V
R/W ( WR )
SS1
). An external positive power supply is required if this
pin and
Jun 2004 P 28/52
D/ C
Auto Address Increment
No
No
Yes
Yes
pin for 6800-series parallel mode,
Rev 1.1
SSD1805 Series