K9F1208U0M- SAMSUNG [Samsung semiconductor], K9F1208U0M- Datasheet - Page 10
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K9F1208U0M-
Manufacturer Part Number
K9F1208U0M-
Description
64M x 8 Bit NAND Flash Memory
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K9F1208U0M-.pdf
(41 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
K9F1208U0M-PCB0
Manufacturer:
SAMSUNG
Quantity:
12 740
Pin Description
Command Latch Enable(CLE)
Address Latch Enable(ALE)
Chip Enable(CE)
Write Enable(WE)
Read Enable(RE)
I/O Port : I/O 0 ~ I/O 7
Write Protect(WP)
Ready/Busy(R/B)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return to the standby mode.
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The WE must be held high when outputs are activated.
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
of RE which also increments the internal column address counter by one.
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
K9F1208U0M-YCB0, K9F1208U0M-YIB0
10
FLASH MEMORY
REA
after the falling edge