HYS6472V16200GU SIEMENS [Siemens Semiconductor Group], HYS6472V16200GU Datasheet - Page 11

• Manufacturer Part Number: HYS6472V16200GU
• Description: 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Notes
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Semiconductor Group
An initial pause of 100 s is required after power-up, then a Precharge All Banks command
must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set
Operation can begin.
AC timing tests have
crossover point. The transition time is measured between
assume
measured with a 50 pF only, without any resisitve termination and with a input signal of 1 V/ns
edge rate between 0.8 V and 2.0 V.
If clock rising time is longer than 1 ns, a time (
Rated at 1.5 V
If
Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
once the Self Refresh Exit command is registered.
Referenced to the time which the output achieves the open circuit condition, not to output
voltage levels.
t
T
CLOCK
INPUT
OUTPUT
is longer than 1 ns, a time (
t
T
t
SETUP
= 1 ns with the AC output load circuit show. Specified
t
HOLD
t
LZ
V
t
AC
IL
= 0.4 V and
1.4 V
t
CL
t
T
– 1) ns has to be added to this parameter.
t
t
OH
CH
t
V
T
IH
t
t
AC
11
HZ
= 2.4 V with the timing referenced to the 1.4 V
HYS 64(72)V16200/3222(0)0/64220GU
t
2.4 V
0.4 V
T
/2 – 0.5) ns has to be added to this parameter.
SPT03404
1.4 V
V
IH
and
t
Measurement conditions for
I/O
AC
V
IL
and
. All AC measurements
SDRAM Modules
t
AC
t
OH
and
parameters are
t
t
RC
50 pF
OH
1998-08-01
is satisfied