HYS64D128320HU-5-C QIMONDA [Qimonda AG], HYS64D128320HU-5-C Datasheet - Page 17

• Manufacturer Part Number: HYS64D128320HU-5-C
• Description: 184-Pin Unbuffered Double Data Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

3.2
Rev. 1.21, 2006-09
03292006-RA8T-MSZL
Parameter
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤
Precharge Floating Standby Current
CS ≥
address and other control inputs changing once per clock cycle;
Precharge Quiet Standby Current
CS ≥
address and other control inputs stable at ≥
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤
Active Standby Current
one bank active; CS ≥
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B;
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
t
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
RC
=
t
V
V
RFCMIN
IH,,MIN
IHMIN
, all banks idle; CKE ≥
, burst refresh
, all banks idle; CKE ≥
I
DD
V
IH,MIN
Specification and Conditions
; CKE ≥
V
V
IH,MIN
IH,MIN
V
IH,MIN
;
V
;
V
IL,MAX
IN
;
V
V
t
=
IH,MIN
ILMAX
RC
V
=
REF
;
t
or ≤
RAS,MAX
V
for DQ, DQS and DM;
IN
=
V
IL,MAX
V
;
REF
I
OUT
23
.
for DQ, DQS and DM.
= 0 mA
V
IN
=
V
REF
for DQ, DQS and DM.
HYS[64/72]D[16/32/128]3xxHU–[5/6]–C
Unbuffered DDR SDRAM Modules
Internet Data Sheet
I
TABLE 14
DD
Conditions
Symbol
I
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2P
DD2F
DD2Q
DD3P
DD3N
DD4R
DD4W
DD5
DD6
DD7