HYS64D128320HU-5-C QIMONDA [Qimonda AG], HYS64D128320HU-5-C Datasheet - Page 4

• Manufacturer Part Number: HYS64D128320HU-5-C
• Description: 184-Pin Unbuffered Double Data Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1.2
The
[5/6]–C, HYS[64/72]D128320HU–[5/6]–C, and are industry
standard
Data Rate SDRAM (UDIMM)
32M × 64 (256 MB), 64M × 64 (512 MB), 128M × 64 (1 GB)
for non-parity and 64M × 72 (512 MB), 128M × 72 (1 GB) for
ECC main memory applications. The memory array is
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example:
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies (for example
Rev. 1.21, 2006-09
03292006-RA8T-MSZL
Product Type
PC3200 (CL=3.0)
HYS64D32301HU–5–C
HYS64D64300HU–5–C
HYS72D64300HU–5–C
HYS64D128320HU–5–C
HYS72D128320HU–5–C
PC2700 (CL=2.5)
HYS64D32301HU–6–C
HYS64D64300HU–6–C
HYS72D64300HU–6–C
HYS64D128320HU–6–C
HYS72D128320HU–6–C
HYS64D128320HU–5–C, indicating Rev.C die are used for SDRAM components.
“30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC
SPD code definition version 0, and the Raw Card used for this module.
HYS64D32301HU–[5/6]–C,
1)
Description
Compliance Code
PC3200U–30331–C3
PC3200U–30331–A1
PC3200U–30331–A1
PC3200U–30331–B2
PC3200U–30331–B2
PC2700U–25331–C3
PC2700U–25331–A1
PC2700U–25331–A1
PC2700U–25331–B2
PC2700U–25331–B2
184-Pin Unbuffered Double
HYS[72/64]D64300HU–
organized
Ordering Information for Lead-Free Products (RoHSCompliant Product)
2)
Description
one rank 256 MB DIMM
one rank 512 MB DIMM
one rank 512 MB ECC-DIMM
two ranks 1 GB DIMM
two ranks 1 GB ECC-DIMM
one rank 256 MB DIMM
one rank 512 MB DIMM
one rank 512 MB ECC-DIMM
two ranks 1 GB DIMM
two ranks 1 GB ECC-DIMM
as
4
designed with 512Mbit Double Data Rate Synchronous
DRAMs. A variety of decoupling capacitors are mounted on
the printed circuit board. The DIMMs feature serial presence
detect (SPD) based on a serial E
pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer
HYS[64/72]D[16/32/128]3xxHU–[5/6]–C
Unbuffered DDR SDRAM Modules
SDRAM Technology
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
2
PROM device using the 2-
Internet Data Sheet
TABLE 2