MT9LSDT1672G-10E MICRON [Micron Technology], MT9LSDT1672G-10E Datasheet - Page 15

• Manufacturer Part Number: MT9LSDT1672G-10E
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: MICRON [Micron Technology]

AC FUNCTIONAL CHARACTERISTICS
(Notes: 1-7)
NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
PARAMETER
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
Data-out to high-impedance from PRECHARGE command
10. Timing actually specified by
11. Based on
12. Timing actually specified by
13. JEDEC and PC100 specify three clocks.
2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device
3. AC characteristics assume
4. In addition to meeting the transition rate specification, the clock and CKE must transit between V
5. Outputs measured at 1.5V with equivalent load:
6. AC timing and I
7. There will be an added one-clock latency at the system level due to the register requiring an added clock cycle.
8. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
9. Timing actually specified by
range (0°C ≤ T
operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the
requirement is exceeded.
between V
transition time is longer than 1ns, then the timing is referenced at V
crossover point.
Q
t
CK = 143 MHz for -13E,
IL
and V
A
DD
≤ +70°C) is ensured.
IH
test have V
) in a monotonic manner.
50pF
t
T = 1ns.
t
t
t
WR.
CKS; clock(s) specified as a reference only at minimum cycle rate.
WR plus
IL
= 0V and V
t
CK = 133 MHz for -133, 100 MHz for -10E.
t
RP; clock(s) specified as a reference only at minimum cycle rate.
IH
= 3V, with timing referenced to 1.5V crossover point. If the input
15
CL = 3
CL = 2
REGISTERED SDRAM DIMMs
IL
(MAX) and V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
t
t
t
t
t
t
t
t
CKED
t
t
t
DQM
DWD
t
t
t
t
MRD
DQD
ROH
ROH
CCD
DQZ
DAL
PED
DPL
BDL
CDL
RDL
IL
(MIN) and no longer at the 1.5V
-133
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
8, 16 MEG x 72
-13E/-10E UNITS
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
IH
and V
t
REF refresh
©1999, Micron Technology, Inc.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ADVANCE
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
IL
(or
NOTES
10, 11
11, 12
11, 12
13
8
9
9
8
8
8
8
8
8
8
8