MT9LSDT1672G-10E MICRON [Micron Technology], MT9LSDT1672G-10E Datasheet - Page 5

• Manufacturer Part Number: MT9LSDT1672G-10E
• Description: SYNCHRONOUS DRAM MODULE
• Manufacturer: MICRON [Micron Technology]

PIN DESCRIPTIONS
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
33, 117, 34, 118, 35, 119,
36, 120, 37, 121, 38, 123
55-58, 60, 65-67, 69-72,
21-22,0 52-53, 105-106,
2-5, 7-11, 13-17, 19-20,
139-142, 144, 149-151,
74-77, 86-89, 91-95,
153-156, 158-161
112-113, 130-131
97-101, 103-104,
42, 79, 125, 163
PIN NUMBERS
28-29, 46-47,
27, 111, 115
165-167
136-137
122, 39
30, 45
128
147
8 1
8 3
WE#, CAS#,
DQ0-DQ63
SYMBOL
BA0, BA1
CK0-CK3
S0#, S2#
DQMB0-
SA0-SA2
CB0-CB7
DQMB7
A0-A11
CKE0
REGE
RAS#
WP
SCL
Output
Output
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Command Inputs: WE#, RAS#, and CAS# (along with S0#, S2#)
define the command being entered.
Clock: CK0 is distributed through an on-board PLL to all devices.
CK1-CK3 are terminated.
Clock Enable: CKE0 activates (HIGH) and deactivates (LOW) the
CK0 signal. Deactivating the clock provides POWER-DOWN and
SELF REFRESH operation (all banks idle) or CLOCK SUSPEND
operation (burst access in progress). CKE0 is synchronous except
after the device enters power-down and self refresh modes,
where CKE0 becomes asynchronous until after exiting the same
mode. The input buffers, including CK0, are disabled during
power-down and self refresh modes, providing low standby
power.
Chip Select: S0#, S2# enable (registered LOW) and disable
(registered HIGH) the command decoder. All commands are
masked when S0#, S2# are registered HIGH. S0#, S2# are
considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-clock
latency) when DQMB is sampled HIGH during a READ cycle.
Bank Address: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
Address Inputs: A0-A11 are sampled during the ACTIVE command
(row-address A0-A11) and READ/WRITE command (column-address
A0-A8/A9, with A10 defining auto precharge) to select one
location out of the memory array in the respective bank. A10 is
sampled during a PRECHARGE command to determine if both
banks are to be precharged (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
Write Protect: Serial presence-detect hardware write protect.
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
Register Enable.
Data I/Os: Data bus.
Check Bits.
5
REGISTERED SDRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
8, 16 MEG x 72
©1999, Micron Technology, Inc.
ADVANCE