HYS64T128920EU-2.5-B2 QIMONDA [Qimonda AG], HYS64T128920EU-2.5-B2 Datasheet - Page 20

• Manufacturer Part Number: HYS64T128920EU-2.5-B2
• Description: 240-Pin unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Rev. 1.0, 2006-10
10202006-L0SM-FEYT
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
input reference level is the crosspoint when in differential strobe mode.
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
@ CL = 3
@ CL = 4
@ CL = 5
V
REF
V
stabilizes. During the period before
TT
.
Symbol
t
t
t
t
t
t
t
CK
CK
CK
RAS
RC
RCD
RP
20
Speed Grade Definition Speed Bins for DDR2–533C
HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
V
REF
stabilizes, CKE = 0.2 x
Max.
8
8
8
70000
—
—
—
Unbuffered DDR2 SDRAM Module
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
V
DDQ
Internet Data Sheet
is recognized as low.
TABLE 14
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
REFI
.