HYS64T128920EU-2.5-B2 QIMONDA [Qimonda AG], HYS64T128920EU-2.5-B2 Datasheet - Page 22

• Manufacturer Part Number: HYS64T128920EU-2.5-B2
• Description: 240-Pin unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1) For details and notes see the relevant Qimonda component data sheet
2)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
6) Inputs are not recognized as valid until
7) The output timing reference voltage level is
8) New units, ‘
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
12) Input waveform timing
13) If
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
15) Input waveform timing
Rev. 1.0, 2006-10
10202006-L0SM-FEYT
Parameter
Internal Read to Precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to read command
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
CKE minimum pulse width ( high and low pulse
width)
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
Minimum time clocks remain ON after CKE
asynchronously drops LOW
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
ps and
t
= - 900 ps – 293 ps = – 1193 ps and
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between
Figure
((L/U/R)DQS / DQS) crossing.
the input signal crossing at the
at the
V
DQSCK.MAX(DERATED)
DDQ
IH.DC.MIN
t
DS
or
= 1.8 V ± 0.1V;
V
t
4.
IL.DC
t
ERR(6- 10PER).MAX
DH
. See
is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
t
CK.AVG
level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between
t
CK
Figure
‘ is used for both concepts. Example:
‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘
=
t
V
DQSCK.MAX
t
4.
DD
t
DS
= + 293 ps, then
DH
= 1.8 V ± 0.1 V. See notes
with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the
with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
–
V
IH.DC
t
ERR(6-10PER).MIN
t
level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
LZ.DQ.MAX(DERATED)
V
t
REF
DQSCK.MIN(DERATED)
V
stabilizes. During the period before
TT
.
= 400 ps + 272 ps = + 672 ps. Similarly,
5)6)7)8)
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
XP
RTP
XSNR
XSRD
XP
XARD
XARDS
CKE
MRD
MOD
OIT
DELAY
= 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
t
CK.AVG
=
t
DQSCK.MIN
+
22
t
ERR.2PER(Min)
–
DDR2–800
7.5
t
200
2
2
8 – AL
3
2
0
0
t
t
Min.
t
RFC
IS
IH
HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2
ERR(6-10PER).MAX
+
+10
t
CK .AVG
.
V
REF
t
CK.AVG
stabilizes, CKE = 0.2 x
+
t
‘ represents the actual
= – 400 ps – 293 ps = – 693 ps and
LZ.DQ
—
—
—
—
—
—
—
12
12
Max.
—
––
Unbuffered DDR2 SDRAM Module
for DDR2–667 derates to
V
IL.AC
t
ERR(6-10per)
level to the differential data strobe
V
V
Unit
ns
ns
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ns
il(DC)MAX
DDQ
of the input clock. (output
t
Internet Data Sheet
CK.AVG
t
is recognized as low.
ERR(6-10PER).MIN
V
and
IL.DC.MAX
of the input clock
Note
8)
1)
1)
31)
1)
1)
t
LZ.DQ.MIN(DERATED)
V
ih(DC)MIN
1)2)3)4)5)6)7)
V
and
IH.AC
= – 272
. See
level