HYS64T64020HM QIMONDA [Qimonda AG], HYS64T64020HM Datasheet - Page 15

• Manufacturer Part Number: HYS64T64020HM
• Description: 214-Pin Micro-DIMM-DDR2-SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.3
This chapter describes the AC characteristics.
3.3.1
This chapter contains the Speed Grade Definition tables.
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Rev. 1.11, 2006-11
03062006-HT1R-Z2PY
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) only.
input reference level is the crosspoint when in differential strobe mode
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
Timing Characteristics
Speed Grade Definitions
@ CL = 3
@ CL = 4
@ CL = 5
Speed Grade Definition Speed Bins for DDR2-667D, DDR2–533C and DDR2–400B
Symbol
t
t
t
t
t
t
t
CK
CK
CK
RAS
RC
RCD
RP
V
REF
V
stabilizes. During the period before
TT
.
DDR2–667D
–3S
5–5–5
Min.
5
3.75
3
45
60
15
15
8
8
70000
—
—
—
Max.
8
15
DDR2–533C
4–4–4
Min.
5
3.75
3.75
45
60
15
15
–3.7
V
REF
Max.
8
8
8
70000
—
—
—
stabilizes, CKE = 0.2 x
HYS64T[32/64]0[0/2]0HM–[3S/3.7/5]–A
Micro-DIMM DDR2 SDRAM Modules
DDR2–400B
–5
3–3–3
Min.
5
5
5
40
55
15
15
Max.
8
8
8
70000
—
—
—
V
DDQ
Internet Data Sheet
is recognized as low.
TABLE 12
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
REFI
.