K9F4008W0A-TIB0 SAMSUNG [Samsung semiconductor], K9F4008W0A-TIB0 Datasheet - Page 11
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K9F4008W0A-TIB0
Manufacturer Part Number
K9F4008W0A-TIB0
Description
512K x 8 bit NAND Flash Memory
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K9F4008W0A-TIB0.pdf
(24 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
K9F4008W0A-TIB0
Manufacturer:
SAM
Quantity:
2 000
Company:
Part Number:
K9F4008W0A-TIB0
Manufacturer:
ATM
Quantity:
3 198
System Interface Using CE don’ t-care.
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
I/O
Figure 3. Program Operation with CE don’ t-care.
I/O
K9F4008W0A-TCB0, K9F4008W0A-TIB0
CLE
CE
WE
Figure 4. Read Operation with CE don’ t-care.
ALE
CE
WE
R/B
CLE
ALE
WE
CE
RE
0
0
~
~
7
7
t
CS
00h
80h
Start Add.(3Cycle)
Start Add.(3Cycle)
t
WP
t
Must be held
low during tR.
CH
t
R
Data Input
11
I/O
CE
RE
0
~
Timing requirements : If CE is is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 60ns.
7
CE don’ t-care
(Max. 60ns)
CE don’ t-care
t
Data Output(sequential)
CEA
t
REA
FLASH MEMORY
Data Input
out
10h