PSD934210JIT STMICROELECTRONICS [STMicroelectronics], PSD934210JIT Datasheet - Page 48

• Manufacturer Part Number: PSD934210JIT
• Description: Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD834F2V
For non-multiplexed 8-bit bus mode, address sig-
nals (A7-A0) are available to Port B in Address Out
Mode.
Note: Do not drive address signals with Address
Out Mode to an external memory device if it is in-
tended for the MCU to Boot from the external de-
vice. The MCU must first Boot from PSD memory
so the Direction and Control register bits can be
set.
Address In Mode
For MCUs that have more than 16 address sig-
nals, the higher addresses can be connected to
Port A, B, C, and D. The address input can be
latched in the Input Macrocell (IMC) by Address
Strobe (ALE/AS, PD0). Any input that is included
in the DPLD equations for the SRAM, or primary or
secondary Flash memory is considered to be an
address input.
Data Port Mode
Port A can be used as a data bus port for a MCU
with a non-multiplexed address/data bus. The
Data Port is connected to the data bus of the MCU.
The general I/O functions are disabled in Port A if
the port is configured as a Data Port.
Peripheral I/O Mode
Peripheral I/O mode can be used to interface with
external peripherals. In this mode, all of Port A
serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O Mode is enabled by set-
ting Bit 7 of the VM Register to a 1. Figure 24
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O Mode is en-
abled. An equation for PSEL0 and/or PSEL1 must
be written in PSDabel. The buffer is tri-stated
when PSEL0 or PSEL1 is not active.
JTAG In-System Programming (ISP)
Port C is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
Figure 24. Peripheral I/O Mode
48/89
RD
PSEL0
PSEL1
VM REGISTER BIT 7
WR
PSEL
DATA BUS
JTAG operations with other functions on Port C
because In-System Programming (ISP) is not per-
formed in normal Operating mode. For more infor-
mation on the JTAG Port, see the section entitled
“Programming In-Circuit using the JTAG Serial In-
terface”, on page 61.
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal read/write bus cycles at the addresses giv-
en in Table 6. The addresses in Table 6 are the off-
sets in hexadecimal from the base of the CSIOP
register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 21, are used for setting the
Port configurations. The default Power-up state for
each register in Table 21 is 00h.
Table 21. Port Configuration Registers (PCR)
Note: 1. See Table 25 for Drive Register bit definition.
Control Register. Any bit reset to 0 in the Control
Register sets the corresponding port pin to MCU I/
O Mode, and a 1 sets it to Address Out Mode. The
default mode is MCU I/O. Only Ports A and B have
an associated Control Register.
D0 - D7
Control
Direction
Drive Select
Register Name
1
A,B
A,B,C,D
A,B,C,D
Port
PA0 - PA7
Write/Read
Write/Read
Write/Read
MCU Access
AI02886