PSD934210JIT STMICROELECTRONICS [STMicroelectronics], PSD934210JIT Datasheet - Page 58

• Manufacturer Part Number: PSD934210JIT
• Description: Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit 256 Kbit Dual Flash Memories and 64 Kbit SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD834F2V
Table 29. Power Management Mode Registers PMMR0
PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo bit (bit 3) in PMMR0. By setting the
bit to 1, the Turbo mode is off and the PLDs con-
sume the specified stand-by current when the in-
puts are not switching for an extended time of
70 ns. The propagation delay time is increased by
10 ns after the Turbo bit is set to 1 (turned off)
Table 30. Power Management Mode Registers PMMR2
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset) pulses do not clear the registers.
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Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
X
APD Enable
X
PLD Turbo
PLD Array clk
PLD MCell clk
X
X
X
X
PLD Array
CNTL0
PLD Array
CNTL1
PLD Array
CNTL2
PLD Array
ALE
PLD Array
DBE
X
0
0 = off Automatic Power-down (APD) is disabled.
1 = on Automatic Power-down (APD) is enabled.
0
0 = on PLD Turbo mode is on
1 = off PLD Turbo mode is off, saving power.
0 = on
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
0 = on CLKIN (PD1) input to the PLD macrocells is connected.
1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
0
0
0
0
0 = on Cntl0 input to the PLD AND Array is connected.
1 = off Cntl0 input to PLD AND Array is disconnected, saving power.
0 = on Cntl1 input to the PLD AND Array is connected.
1 = off Cntl1 input to PLD AND Array is disconnected, saving power.
0 = on Cntl2 input to the PLD AND Array is connected.
1 = off Cntl2 input to PLD AND Array is disconnected, saving power.
0 = on ALE input to the PLD AND Array is connected.
1 = off ALE input to PLD AND Array is disconnected, saving power.
0 = on DBE input to the PLD AND Array is connected.
1 = off DBE input to PLD AND Array is disconnected, saving power.
0
Not used, and should be set to zero.
Not used, and should be set to zero.
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo bit is 0.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
Not used, and should be set to zero.
when the inputs change at a composite frequency
of less than 15 MHz. When the Turbo bit is reset to
0 (turned on), the PLDs run at full power and
speed. The Turbo bit affects the PLD’s DC power,
AC power, and propagation delay.
Blocking MCU control signals with the bits of
PMMR2 can further reduce PLD AC power con-
sumption.
1
1