KMM374S403CT SAMSUNG [Samsung semiconductor], KMM374S403CT Datasheet - Page 2

• Manufacturer Part Number: KMM374S403CT
• Description: PC100 SDRAM MODULE
• Manufacturer: SAMSUNG [Samsung semiconductor]

KMM374S403CT
KMM374S403CT SDRAM DIMM
GENERAL DESCRIPTION
Dynamic RAM high density memory module. The Samsung
KMM374S403CT consists of eighteen CMOS 2M x 8 bit Syn-
chronous DRAMs in TSOP-II 400mil package and a 1K or 2K
EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parellel for each SDRAM.
The KMM374S403CT is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
4Mx72 SDRAM DIMM with ECC based on 2Mx8, 4K Refresh, 3.3V Synchronous DRAMs with SPD
PIN CONFIGURATIONS (Front Side / Back Side)
Synchronous design allows precise cycle control with the use of
Pin
The Samsung KMM374S403CT is a 4M bit x 72 Synchronous
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
DQM0
Front
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
CB0
CB1
V
V
V
V
V
V
WE
NC
NC
DD
DD
DD
SS
SS
SS
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
A10/AP
DQM1
DQM2
DQM3
Front
DQ16
DQ17
CLK0
*BA1
CS0
CS2
CB2
CB3
V
V
V
V
V
V
DU
DU
DU
NC
NC
A0
A2
A4
A6
A8
DD
DD
DD
SS
SS
SS
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
**SDA
**SCL
DQ18
DQ19
DQ20
*V
CKE1
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Front
CLK2
V
V
V
V
V
V
WP
NC
NC
DD
REF
DD
DD
SS
SS
SS
100
101
102
103
104
105
106
107
108
109
110
111
112
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
DQM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
Back
CAS
CB4
CB5
V
V
V
V
V
V
NC
NC
SS
DD
SS
DD
SS
DD
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Pin
DQM5
DQM6
DQM7
CKE0
DQ48
DQ49
CLK1
Back
*A11
*A12
*A13
RAS
CS1
BA0
CS3
CB6
CB7
V
V
V
V
V
NC
NC
A1
A3
A5
A7
A9
DD
DD
SS
SS
SS
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
FEATURE
• Performance range
• Burst Mode Operation
• Auto & Self Refresh Capability (4096 cycles / 64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the
• Serial Presence Detect with EEPROM
• PCB : Height(1,250mil), double sided component
KMM374S403CT-G8
KMM374S403CT-GH
KMM374S403CT-GL
Latency (Access from column address)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
system clock
DQ50
DQ51
DQ52
*V
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
**SA0
**SA1
**SA2
Back
CLK3
V
V
V
V
V
V
NC
NC
NC
REF
DD
SS
SS
DD
SS
DD
0.3V power supply
PIN NAMES
*
** These pins should be NC in the system
PC100 SDRAM MODULE
Pin Name
A0 ~ A10/AP
BA0
DQ0 ~ DQ63
CB0 ~ 7
CLK0 ~ CLK3
CKE0 ~ CKE1
CS0 ~ CS3
RAS
CAS
WE
DQM0 ~ 7
V
V
*V
SDA
SCL
SA0 ~ 2
WP
DU
NC
DD
SS
These pins are not used in this module.
which does not support SPD.
REF
Max Freq. (Speed)
100MHz (10ns)
125MHz (8ns)
100MHz (10ns)
Function
Address Input (multiplexed)
Select Bank
Data Input / Output
Check Bit (data-in / data-out)
Clock Input
Clock Enable Input
Chip Select Input
Row Address Storbe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
Power Supply for Reference
Serial Data I/O
Serial Clock
Address in EEPROM
Write Protection
Don t use
No Connection
REV. 1 Mar. '98