KMM374S403CT SAMSUNG [Samsung semiconductor], KMM374S403CT Datasheet - Page 3

• Manufacturer Part Number: KMM374S403CT
• Description: PC100 SDRAM MODULE
• Manufacturer: SAMSUNG [Samsung semiconductor]

KMM374S403CT
PIN CONFIGURATION DESCRIPTION
CLK
CS
CKE
A0 ~ A10/AP
BA0
RAS
CAS
WE
DQM0 ~ 7
DQ0 ~ 63
CB0 ~ 7
WP
V
DD
/V
Pin
SS
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Check bit
Write Protection
Power Supply/Ground
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+t
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
WP pin is connected to V
When WP is "high", EEPROM Programming will be inhibited and the entire memory will
Power and ground for the input buffers and the core logic.
be write - protected.
CC
SHZ
.
after the clock and masks the output.
SS
prior to valid command.
Input Function
PC100 SDRAM MODULE
REV. 1 Mar. '98
RAS low.
CAS low.