ST7036-0A ETC [List of Unclassifed Manufacturers], ST7036-0A Datasheet - Page 15

• Manufacturer Part Number: ST7036-0A
• Description: Dot Matrix LCD Controller/Driver
• Manufacturer: ETC [List of Unclassifed Manufacturers]

ST7036
· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to
· Synchronization: procedure to synchronize the clock signals of two or more devices.
A
Acknowledge signal (ACK) is not BF signal in parallel interface.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the
transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master
receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP
condition. Acknowledgement on the I
V1.1
do so and the message is not corrupted
CKNOWLEDGE
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
SCL
SDA
SCL
SDA
START condition
Fig .2 Definition of START and STOP conditions
S
RECEIVER (1)
0111100
SLAVE
2
C Interface is illustrated in Fig.4.
data valid
Fig .3 System configuration
data line
stable;
Fig .1 Bit transfer
RECEIVER (2)
0111101
SLAVE
allowed
change
of data
15/72
RECEIVER (3)
0111110
SLAVE
STOP condition
P
RECEIVER (4)
0111111
SLAVE
2003/12/24