ST7036-0A ETC [List of Unclassifed Manufacturers], ST7036-0A Datasheet - Page 16

• Manufacturer Part Number: ST7036-0A
• Description: Dot Matrix LCD Controller/Driver
• Manufacturer: ETC [List of Unclassifed Manufacturers]

ST7036
I
The ST7036 supports command, data write addressed slaves on the bus.
Before any data is transmitted on the I
addresses (0111100 to 0111111) are reserved for the ST7036. The R/W is assigned to 0 for Write only.
The I
The sequence is initiated with a START condition (S) from the I
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I
acknowledgement, one or more command words follow which define the status of the addressed slaves.
A command word consists of a control byte, which defines Co and RS, plus a data byte.
The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a
cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command
or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte,
depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set
to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is
automatically updated and the data is directed to the intended ST7036i device. If the RS bit of the last control byte is set to
logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received
commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I
INTERFACE-bus master issues a STOP condition (P).
V1.1
2
C Interface protocol
2
C Interface protocol is illustrated in Fig.5.
BY TRANSMITTER
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
Fig .4 Acknowledgement on the IIC Interface
condition
START
2
S
C Interface, the device, which should respond, is addressed first. Four 7-bit slave
1
16/72
2
2
C Interface master, which is followed by the slave address.
not acknowledge
acknowledge
8
acknowledgement
clock pulse for
9
2
C Interface transfer. After
2003/12/24
2
C