ST7036-0A ETC [List of Unclassifed Manufacturers], ST7036-0A Datasheet - Page 21

• Manufacturer Part Number: ST7036-0A
• Description: Dot Matrix LCD Controller/Driver
• Manufacturer: ETC [List of Unclassifed Manufacturers]

ST7036
The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate
240/250/248/256 5 x 8 dot character patterns(select by OPR1/2 ITO pin). User-defined character patterns are
also available by mask-programmed ROM.
In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight
character patterns can be written.
Write into DDRAM the character codes at the addresses shown as the left column of Table 5 to show the
character patterns stored in CGRAM.
See Table 5 for the relationship between CGRAM addresses and data and display patterns. Areas that are not
used for display can be used as general data RAM.
In the ICON RAM, the user can rewrite icon pattern by program.
There are totally 80 dots for icon can be written.
See Table 6 for the relationship between ICON RAM address and data and the display patterns.
The timing generation circuit generates timing signals for the operation of internal circuits such as
DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU
access are generated separately to avoid interfering with each other. Therefore, when writing data to
DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than
the display area.
LCD Driver circuit has 17 common and 100 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 100 bit segment latch serially, and then it is stored to 100 bit shift latch. When each common is
selected by 17 bit common register, segment data also output through segment driver from 100 bit segment
latch. In case of 1-line display mode, COM1 ~ COM8(with COMI) have 1/9 duty, and in 2-line mode, COM1 ~
COM16(with COMI) have 1/17 duty ratio.
LCD Driver circuit has 25 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM/ICON
is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is
selected by 25 bit common register, segment data also output through segment driver from 80 bit segment latch.
In case of 3-line display mode, COM1 ~ COM24(with COMI) have 1/25 duty.
It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at
the display data RAM address set in the address counter.
V1.1
Character Generator ROM (CGROM)
Character Generator RAM (CGRAM)
ICON RAM
Timing Generation Circuit
LCD Driver Circuit(N3=0)
LCD Driver Circuit(N3=1)
Cursor/Blink Control Circuit
COM/SEG Output pins
VDD
VSS
N3
COMI1
COMI1
NC
[5:12]
COM
COM
COM
[1:8]
[1:8]
Table 3. COM/SEG output define
COM[4:1]
+ COMI1
SEG
SEG
[1:5]
[1:5]
[6:10]
[6:10]
21/72
SEG
SEG
NC
[11:90]
[11:90]
[1:80]
SEG
SEG
SEG
[91:96]
[91:96]
SEG
SEG
NC
[97:100]
[97:100]
[13:16]
COM
SEG
SEG
[17:24]
[9:16]
[9:16]
COM
COM
COM
2003/12/24
COMI2
COMI2
COMI2