ST7036-0A ETC [List of Unclassifed Manufacturers], ST7036-0A Datasheet - Page 26

• Manufacturer Part Number: ST7036-0A
• Description: Dot Matrix LCD Controller/Driver
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Clear
Display
Return
Home
Entry Mode
Set
Display
ON/OFF
Cursor or
Display Shift
Function Set
Set CGRAM
Set DDRAM
Address
Read Busy
Flag and
Address
Write Data
to RAM
Read Data
from RAM
Instruction
ST7036
There are four categories of instructions that:
(when “EXT” option pin connect to V
Note:
Be sure the ST7036 is not in the busy state (BF = 0) before sending an instruction from the MPU to the ST7036.
If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction
will take much longer than the instruction time itself. Refer to Instruction Table for the list of each instruction
execution time.
V1.1
Instructions
Designate ST7036 functions, such as display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Others
instruction table at “Normal mode”
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
D7
D7
0
0
0
0
0
0
0
1
Instruction Code
AC6 AC5 AC4 AC3 AC2 AC1 AC0
D6
D6
0
0
0
0
0
0
1
AC5 AC4 AC3 AC2 AC1 AC0
D5
D5
0
0
0
0
0
1
DL
D4
D4
DD
0
0
0
0
1
, the instruction set follow below table)
S/C R/L
D3
D3
N
0
0
0
1
D2
D2
D
0
0
1
X
I/D
D1
D1
C
X
X
0
1
26/72
D0
D0
1
X
S
B
X
X
Write "20H" to DDRAM. and set
DDRAM address to "00H" from AC
Set DDRAM address to "00H" from
AC and return cursor to its original
position if shifted. The contents of
DDRAM are not changed.
Sets cursor move direction and
specifies display shift. These
operations are performed during
data write and read.
D=1:entire display on
C=1:cursor on
B=1:cursor position on
S/C and R/L:
Set cursor moving and display shift
control bit, and the direction, without
changing DDRAM data.
DL: interface data is 8/4 bits
N: number of line is 2/1
Set CGRAM address in address
counter
Set DDRAM address in address
counter
Whether during internal operation or
not can be known by reading BF.
The contents of address counter
can also be read.
Write data into internal RAM
(DDRAM/CGRAM)
Read data from internal RAM
(DDRAM/CGRAM)
Description
OSC=
380kHz
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
26.3 µs 18.5 µs 14.3 µs
1.08
1.08
ms
ms
0
Execution Time
Instruction
OSC=
540kHz
0.76
0.76
ms
ms
2003/12/24
0
OSC=
700kHz
0.59
0.59
ms
ms
0