H5TQ1G43BFR HYNIX [Hynix Semiconductor], H5TQ1G43BFR Datasheet
H5TQ1G43BFR
Related parts for H5TQ1G43BFR
H5TQ1G43BFR Summary of contents
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... DDR3 SDRAM Lead-Free&Halogen-Free H5TQ1G43BFR-xxC H5TQ1G83BFR-xxC H5TQ1G63BFR-xxC *Hynix Semiconductor reserves the right to change products or specifications without notice Rev. 1.0 / Dec. 2009 (RoHS Compliant) 1Gb DDR3 SDRAM 1 ...
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Revision History Revision No. 0.1 Preliminary Initial Release 0.2 Added IDD Spec 0.3 Package Dimension Notation change - No Physical change 0.4 Updated IDD Specification 1.0 JEDEC Update Rev. 1.0 / Dec. 2009 History Draft Date Sep. 2008 Jan. 2009 ...
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... Description The H5TQ1G43BFR-xxC, H5TQ1G83BFR-xxC and H5tQ1G63BFR-xxC are a 1,073,741,824-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 1Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it ...
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... ORDERING INFORMATION Part No. H5TQ1G43BFR-*xxC H5TQ1G83BFR-*xxC H5TQ1G63BFR-*xxC * xx means Speed Bin Grade OPERATING FREQUENCY Speed Grade (Marking) CL5 CL6 -G7 O -H9 O Rev. 1.0 / Dec. 2009 Configuration Frequency [MHz] CL7 CL8 CL9 CL10 Package 256M x 4 78ball FBGA 128M x 8 ...
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Package Ballout/Mechanical Dimension x4 Package Ball out (Top view): 78ball FBGA Package (no support balls VSS VDD B VSS VSSQ C VDDQ DQ2 D VSSQ NF E VREFDQ VDDQ F NC VSS G ODT VDD H NC ...
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Package Ball out (Top view): 78ball FBGA Package (no support balls VSS VDD B VSS VSSQ C VDDQ DQ2 D VSSQ DQ6 E VREFDQ VDDQ F NC VSS G ODT VDD VSS ...
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Package Ball out (Top view): 96ball FBGA Package (no support balls VDDQ DQU5 B VSSQ VDD C VDDQ DQU3 D VSSQ VDDQ E VSS VSSQ F VDDQ DQL2 G VSSQ DQL6 H VREFDQ VDDQ J NC VSS ...
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Pin Functional Description Symbol Type Clock: CK and CK are differential clock inputs. All address and control input signals are CK, CK Input sampled on the crossing of the positive edge of CK and negative edge of CK. Clock Enable: ...
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Symbol Type Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET Input RESET is a CMOS rail-to-rail signal with DC high and low at ...
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ROW AND COLUMN ADDRESS TABLE 1Gb Configuration # of Banks Bank Address Auto precharge BL switch on the fly Row Address Column Address 1 Page size Note1: Page size is the number of bytes of data delivered from the array ...
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Absolute Maximum Ratings Absolute Maximum DC Ratings Symbol Parameter VDD Voltage on VDD pin relative to Vss VDDQ Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss IN OUT T Storage Temperature ...
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AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Symbol Parameter VDD Supply Voltage VDDQ Supply Voltage for Output Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks ...
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IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the setup and test load for IDD and ...
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RESET CK/CK CKE CS RAS, CAS ODT Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be ...
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol RCD RAS n RP 1KB page size n FAW 2KB page size 1KB page size n RRD 2KB page size n -512Mb ...
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Symbol Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL Bank Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; DD2N Bank Activity: all banks closed; Output ...
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Symbol Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL DD3P Bank Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: ...
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Symbol Self-Refresh Current: Extended Temperature Range Auto Self-Refresh (ASR): Disabled CASE CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL DD6ET Address, Bank ...
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Table 3 - IDD0 Measurement-Loop Pattern 0 0 1,2 3,4 ... nRAS ... 1*nRC+0 1*nRC+1, 2 1*nRC+3, 4 ... 1*nRC+nRAS ... 1 2*nRC 2 4*nRC 3 6*nRC 4 8*nRC 5 10*nRC 6 12*nRC 7 14*nRC a) DM must be driven ...
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Table 4 - IDD1 Measurement-Loop Pattern 0 0 1,2 3,4 ... nRCD ... nRAS ... 1*nRC+0 1*nRC+1,2 1*nRC+3,4 ... 1*nRC+nRCD ... 1*nRC+nRAS ... 1 2*nRC 2 4*nRC 3 6*nRC 4 8*nRC 5 10*nRC 6 12*nRC 7 14*nRC a) DM must ...
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Table 5 - IDD2N and IDD3N Measurement-Loop Pattern 4-7 repeat Sub-Loop 0, use BA[2: instead 2 8-11 repeat Sub-Loop 0, use BA[2: instead 3 12-15 repeat Sub-Loop 0, use BA[2:0] ...
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Table 7 - IDD4R and IDDQ24RMeasurement-Loop Pattern 2 6,7 1 8-15 repeat Sub-Loop 0, but BA[2: 16-23 repeat Sub-Loop 0, but BA[2: 24-31 repeat Sub-Loop 0, but BA[2:0] = ...
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Table 8 - IDD4W Measurement-Loop Pattern 2 6,7 1 8-15 2 16-23 3 24-31 4 32-39 5 40-47 6 48-55 7 56- must be driven LOW all the time. DQS, DQS are used ...
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Table 10 - IDD7 Measurement-Loop Pattern ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0 ... nRRD nRRD+1 1 nRRD+2 ... 2 2*nRRD 3 3*nRRD 4*nRRD 4 5 nFAW 6 nFAW+nRRD 7 ...
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IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. I Specification DD Speed Grade DDR3 - 1066 Bin Symbol I DD0 I DD1 I DD2N I DD2NT I DD2P0 I DD2P1 I DD2Q ...
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Input/Output Capacitance Parameter Symbol Input/output capacitance C (DQ, DM, DQS, DQS, IO TDQS, TDQS) Input capacitance, CK and Input capacitance delta C DCK CK and CK Input capacitance delta, C DDQS DQS and DQS Input capacitance C ...
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Standard Speed Bins DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-800 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 30. Speed Bin CL - nRCD - nRP ...
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DDR3-1066 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 30. Speed Bin CL - nRCD - nRP Parameter Symbol Internal read command first data ACT to internal read or t RCD write delay ...
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DDR3-1333 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 30. Speed Bin CL - nRCD - nRP Parameter Symbol Internal read t AA command to first data ACT to internal read or t RCD write delay ...
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Speed Bin Table Notes Absolute Specification ( OPER 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak- ing a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting ...
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Package Dimensions Package Dimension(x4/x8); 78Ball Fine Pitch Ball Grid Array Outline 7.500 0.100 A1 CORNER (1.875) INDEX AREA 3.0 X 5.0 MIN FLAT AREA 0.800 6.400 2.100 0.100 0.800 ...
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Package Dimension(x16); 96Ball Fine Pitch Ball Grid Array Outline 7.500 0.100 A1 CORNER INDEX AREA (1.875) 3.0 X 5.0 MIN FLAT AREA TOP 0.800 6.400 2.100 0.100 0.800 ...