H5TQ1G43BFR HYNIX [Hynix Semiconductor], H5TQ1G43BFR Datasheet - Page 30

• Manufacturer Part Number: H5TQ1G43BFR
• Description: 1Gb DDR3 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Speed Bin Table Notes
Absolute Specification (T
Rev. 1.0 / Dec. 2009
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-
3. tCK(AVG).MAX limits: Calculate tCK (AVG) = tAA.MAX / CLSELECTED and round the resulting tCK
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
8. Hynix DDR3L SRAM devices support down binning to CL=7 and CL=9, and tAA/tRCD/tRP satisfy mini-
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
ing a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as
requirements from CWL setting.
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK (AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL
[nCK] = tAA [ns] / tCK (AVG) [ns], rounding up to the next ‘Supported CL’.
(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CLSELECTED.
table which are not subject to Production Tests but verified by Design/Characterization.
table which are not subject to Production Tests but verified by Design/Characterization.
table which are not subject to Production Tests but verified by Design/Characterization.
mum value of 13.125ns. SPD settings are also programmed to match. For example, DDR3 1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3 1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
OPER
; V
DDQ
= V
DD
= 1.35V +0.100 / - 0.067 V);
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