H5TQ1G43BFR HYNIX [Hynix Semiconductor], H5TQ1G43BFR Datasheet - Page 27
H5TQ1G43BFR
Manufacturer Part Number
H5TQ1G43BFR
Description
1Gb DDR3 SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.H5TQ1G43BFR.pdf
(32 pages)
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For specific Notes See “Speed Bin Table Notes” on page 30.
Standard Speed Bins
DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
Rev. 1.0 / Dec. 2009
ACT to internal read or write delay time
ACT to ACT or REF command period
Internal read command to first data
CL = 5
CL = 6
ACT to PRE command period
PRE command period
Supported CWL Settings
Parameter
Supported CL Settings
CL - nRCD - nRP
Speed Bin
CWL = 5
CWL = 5
Symbol
t
t
CK(AVG)
CK(AVG)
t
t
t
t
t
RCD
RAS
AA
RP
RC
min
52.5
37.5
2.5
15
15
15
DDR3-800E
Reserved
6-6-6
6
5
9 * tREFI
max
3.3
20
—
—
—
Unit
n
n
ns
ns
ns
ns
ns
ns
ns
CK
CK
1, 2, 3, 4
Notes
1, 2, 3
27
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