ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 119

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
SERIAL PERIPHERAL INTERFACE (SPI)
The ADE7566/ADE7569 integrate a complete hardware serial
peripheral interface on-chip. The SPI is full duplex so that 8 bits
of data are synchronously transmitted and simultaneously
received. This SPI implementation is double buffered, allowing
users to read the last byte of received data while a new byte is
shifted in. The next byte to be transmitted can be loaded while
the current byte is shifted out.
The SPI port can be configured for master or slave operation.
The physical interface to the SPI is via MISO (P0.5), MOSI (P0.4),
SCLK (P0.6), and SS (P0.7) pins, while the firmware interface is
SPI SFR REGISTER LIST
Table 133. SPI SFR Register List
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Table 134. SPI/I
Bit No.
7 to 0
Table 135. SPI/I
Bit No.
7 to 0
Mnemonic
SPI2CTx
Mnemonic
SPI2CRx
2
2
C Transmit Buffer SFR (SPI2CTx, 0x9A)
C Receive Buffer SFR (SPI2CRx, 0x9B)
Default
0
Default
0
Name
SPI2CTx
SPI2CRx
SPIMOD1
SPIMOD2
SPISTAT
Description
SPI or I
input. When a write is requested, the FIFO output is sent on the SPI or I
Description
SPI or I
to SPI2CRx SFR. A new data byte from the SPI or I
2
2
C Transmit Buffer. When SPI2CTx SFR is written, its content is transferred to the transmit FIFO
C Receive Buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is transferred
R/W
W
R
R/W
R/W
R/W
Length
8
8
8
8
8
Rev. PrA | Page 119 of 136
Default
0
0x10
0
0
via the SPI Configuration Register SFR (SPIMOD1, 0xE8), the
SPI Configuration Register SFR (SPIMOD2, 0xE9), the SPI
Interrupt Status Register SFR (SPISTAT, 0xEA), the SPI/I
Transmit Buffer SFR (SPI2CTx, 0x9A), and the SPI/I
Buffer SFR (SPI2CRx, 0x9B).
Note that the SPI pins are shared with the I
user can enable only one interface at a time. The SCPS bit in the
Configuration SFR (CFG, 0xAF) selects which peripheral is
active.
2
C bus is written to the FIFO input.
Description
SPI/I
SPI/I
SPI Configuration Register (see Table 136).
SPI Configuration Register. (see Table 137).
SPI/I
2
2
2
C Data Out Register (see Table 134).
C Data in Register (see Table 135).
C Interrupt Status Register (see Table 138).
2
C bus.
ADE7566/ADE7569
2
C pins. Therefore, the
2
C Receive
2
C