ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 88

• Manufacturer Part Number: ADE7566ASTZF8-RL2
• Description: Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
• Manufacturer: AD [Analog Devices]

ADE7566/ADE7569
Table 75. LCD Configuration X SFR (LCDCONX, 0x9C)
Bit No.
7
6
5 to 0
Table 76. LCD Bias Voltage When Contrast Control Is Enabled
BIASLVL[5]
0
1
Table 77. LCD Configuration Y SFR (LCDCONY, 0xB1)
Bit No.
7
6
5 to 2
1
0
Table 78. LCD Clock SFR (LCDCLK, 0x96)
Bit No.
7 to 6
5 to 4
3 to 0
Mnemonic
Reserved
INV_LVL
Reserved
UPDATEOVER
REFRESH
Mnemonic
BLKMOD[1:0]
BLKFREQ[1:0]
FD[3:0]
Mnemonic
Reserved
EXTRES
BIASLVL[5:0]
V
V
V
A
REF
REF
(V)
×
×
⎛
⎜
⎝
BLVL
1
Default
0
0
0
0
0
Default
0
0
0
+
31
Default
0
0
0
BLVL
[
4:0
31
]
[
4:0
]
Description
This bit should be kept cleared for proper operation.
Frame Inversion Mode Enable Bit. If this bit is set, frames are inverted every other frame. If this
bit is cleared, frames are not inverted.
These bits should be kept cleared for proper operation.
Update Finished Flag Bit. This bit is updated by LCD driver. When set, this bit indicates that the
LCD memory has been updated and a new frame has begun.
Refresh LCD Data Memory Bit. This bit should be set by user. When set, the LCD driver does not
use the data in the LCD data registers to update display. The LCD data registers can be updated
by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update
display at the next frame.
Description
Blink Mode Clock Source Configuration Bits.
BLKMOD[1:0]
00
01
10
11
Blink Rate Configuration Bits. These bits control the LCD blink rate if BLKMOD[1:0] = 11
BLKFREQ[1:0]
00
01
10
11
LCD Frame Rate Selection Bits. See Table 79 and Table 80.
⎞
⎟
⎠
Description
Reserved.
External Resistor Ladder Selection Bit.
EXTRES
0
1
Bias Level Selection Bits. See Table 76.
Result
External resistor ladder is disabled. Charge pump is enabled.
External resistor ladder is enabled. Charge pump is disabled.
Rev. PrA | Page 88 of 136
Result
The blink rate is controlled by software. The display is off.
The blink rate is controlled by software. The display is on.
The blink rate is 2 Hz
The blink rate is set by BLKFREQ[1:0]
Result (Blink Rate)
1 Hz
1/2 Hz
1/3 Hz
1/4 Hz
V
V
V
B
B
B
= V
= V
A
A
1/2 Bias
V
V
V
C
C
C
= 2 x V
= 2 x V
A
A
Preliminary Technical Data
V
V
V
B
B
B
= 2 x V
= 2 x V
A
A
1/3 Bias
V
V
V
C
C
C
= 3 x V
= 3 x V
A
A