ADE7566ASTZF8-RL2 AD [Analog Devices], ADE7566ASTZF8-RL2 Datasheet - Page 27

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ADE7566ASTZF8-RL2

Manufacturer Part Number
ADE7566ASTZF8-RL2
Description
Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
Manufacturer
AD [Analog Devices]
Datasheet
Preliminary Technical Data
POWER SUPPLY MONITOR INTERRUPT (PSM)
The power supply monitor interrupt (PSM) alerts the 8052 core
of power supply events. The PSM interrupt is disabled by
default. Setting the EPSM bit in the Interrupt Enable and
Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt.
IPSME ADDR. 0xEC
IPSMF ADDR. 0xF8
IEIP2 ADDR. 0xA9
EVDCIN
FVDCIN
EVSW
ESAG
FVSW
EBSO
EPSR
FSAG
FBSO
FPSR
EBAT
FBAT
RESERVED
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN
FPSR
EPSR
RESERVED
FPSM
PTI
RESERVED
ESAG
FSAG
Figure 23. PSM Interrupt Sources
FPSM
EPSM
Rev. PrA | Page 27 of 136
RESERVED
RESERVED
PSI
The Power Management Interrupt Enable SFR (IPSME, 0xEC)
controls the events that result in a PSM interrupt. Figure 23 is a
diagram illustrating how the PSM interrupt vector is shared
among the PSM interrupt sources. The PSM interrupt flags are
latched and must be cleared by writing to the flag register.
EVSW
FVSW
EADE
TRUE?
PENDING PSM
INTERRUPT
EBAT
FBAT
ETI
EBSO
FBSO
EPSM
ADE7566/ADE7569
EVDCIN
FVDCIN
ESI

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