LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 23

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

9.6.1.3 Threshold and Output
• The ‘Sound’ threshold level is set with YLEVEL[3:0] register.
• The YLEVEL[3:0] register can adjust the level from -60dBFS to -30dBFS in 2dBFS steps.
• At YLEVEL[3:0] register initial value, ‘Sound’ is judged when the signal is larger than -60dBFS.
• The results of judging the data after passing through the HPF are output from DSTATE pin and ODATAM register.
• When a signal that is larger than the threshold level set by YLEVEL[3:0] register is detected, DSTATE outputs “H.”
9.6.2 ‘Silence’ Detection
• The ‘Silence’ detection operates in normal operation mode, and “SDMODE=0” is set.
• The ‘Silence’ threshold level is set with NLEVEL[3:0] register.
• The NLEVEL[3:0] register can adjust the level from -60dBFS to -30dBFS in 2dBFS steps.
• At NLEVEL[3:0] register initial value, ‘Silence’ is judged when the signal is smaller than -60dBFS.
• The results of judging the data after passing through the HPF are output from DSTATE pin and ODATAM register.
• When a signal that is smaller than the threshold level set by NLEVEL[3:0] register is detected, DSTATE outputs “L.”
9.6.3 DSTATE Output
• The DSTATE output polarity can be changed with DSTATEP.
• The DSTATE pin status can also be read from ODATAM register.
• When ADC operation is stopped, DSTATE outputs “L.”
• ‘Sound’ or ‘Silence’ detection can be performed for digital audio data in addition to analog audio data. See below for
9.7 Reset Process
• When the PLL is locked by setting “SYSRST=1” or “ADCOPR[1:0]=00”, the ADC is in the reset status. When
• ‘Sound’ or ‘Silence’ detection flag DSTATE after reset cancel is output after progress 32768/fs.
further details, “12. Digital Audio Data Detection”.
“ADBMOD=0” is set, 16384/fs period is normally necessary for the reset cancel. If “ADBMOD=1” is set, it has not
wait time. The digital data is output after fade-in processing after reset cancel.
DSTATE Output
ADC State
DATAOUT
PLL State
DSTATE
MUTEB
H
L
(Analog data detection flag)
Table 9.7 Analog Data and DSTATE Pin Output Status (When “DSTATEP=0”)
ADC output
Figure 9.5 ADC Reset Processing Timing (When “ADBMOD=0”)
Operation
Smaller than the value set by the NLEVEL register or the
ADC is reset
Larger than the value set by the NLEVEL register
Unlock
Flag
SDMODE=0 (‘Silence’ detection)
fs=48kHz: 341ms
fs=96kHz: 170ms
LC89075W-H
DIR output
Reset
Lock
“ADBMOD=0”
16384/f
32768/fs
Smaller than the value set by the YLEVEL register or the
ADC is reset
Larger than the value set by the YLEVEL register
Fade in
Operation
SDMODE=1 (‘Sound’ detection)
Unlock
ADC output
fs=48kHz: 682ms
fs=96kHz: 341ms
Flag
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