LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 59

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

• When input fs calculation cannot be done by “RXCKAT=0”, the PLL clock is set to 256fs output.
• Set the RXCKAT,RXCKDEV[1:0] and RXMCK[1:0] register while the PLL is unlocked. This setting is executed
Register name
Initial value
Setting
after the PLL is locked. However, after PLL is locked, RXMCK[1:0] register can change by RXCKMU register.
RXCKAT
RXCKDV[1:0] PLL lock time MCKOUT output setting when RXCKAT is set to 0
RXMCK[1:0]
RXCKWT[1:0] Clock switching wait time setting
0Ah
RXCKWT1
PLL clock lock frequency setting
PLL lock time MCKOUT output setting when RXCKAT is set to 1
R/W
D7
0
00: 256fs output (initial value)
01: 512fs output
10: 128fs output
11: Reserved
00: 512fs output: When receiving 32kHz, 44.1kHz, 48kHz (initial value)
01: 256fs output: When receiving 32kHz, 44.1kHz, 48kHz
10: 512fs output: When receiving 32kHz, 44.1kHz, 48kHz
11: 256fs output: When receiving 32kHz, 44.1kHz, 48kHz
00: The clocks is switched 2.7ms after PLL locked status is judged (initial value).
01: The clock is switched 1.3ms after PLL locked status is judged.
10: The clock is switched 0.7ms after PLL locked status is judged.
11: Reserved
0: Automatic control (initial value)
1: Manual setting
RXCKWT0
256fs output: When receiving 64kHz, 88.2kHz, 96kHz
128fs output: When receiving 128kHz, 176.4kHz, 192kHz
256fs output: When receiving 64kHz, 88.2kHz, 96kHz
128fs output: When receiving 128kHz, 176.4kHz, 192kHz
512fs output: When receiving 64kHz, 88.2kHz, 96kHz
128fs output: When receiving 128kHz, 176.4kHz, 192kHz
512fs output: When receiving 64kHz, 88.2kHz, 96kHz
128fs output: When receiving 128kHz, 176.4kHz, 192kHz
R/W
D6
0
Address: 0Ah; DIR Clock Setting
RXMCK1
R/W
D5
0
LC89075W-H
RXMCK0
R/W
D4
0
RXCKDV1
R/W
D3
0
RXCKDV0
R/W
D2
0
D1
R
0
0
No.A1858-59/69
RXCKAT
R/W
D0
0