LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 42

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

14. Microcontroller Interface (CSB, SCK, SI, SO, INTB)
• The LC89075W-H is controlled via SPI (Serial Peripheral Interface, Modes 0 & 3).
• This interface consists of CSB: chip select, SCK: serial clock input, SI: data input, and SO: data output.
• SI consists of read/write (R/W), “0” data (2 bits), register address (A[4:0]), and control data (8 bits × n, [MSB:LSB]).
• SI has to set to “L” input when turning the power on.
• Data read is performed by R/W=1 and the data is output from SO after the register address is set.
• SO outputs high impedance when R/W=0 or when CSB is “H”.
• The LC89075W-H incorporates an address counter, and is controlled in the current address access mode that performs
14.1 Current Address Access Mode
• This mode holds the A[4:0] address value in the address counter for both read and write, and increments the address
• The increment function is executed while CSB is “L”, but when the write address exceeds 0Eh or the read address
R/W is written when “0”, or read when “1”.
read/write while automatically incrementing the address, or in the random address access mode that reads/writes the
data for an arbitrary address.
value by “+1” at the timing when D0 is loaded to the register. D[7:0] data write is executed at this same timing, and
data write is performed in byte units thereafter (at the timing indicated by ↑ in Fig. 14.2).
exceeds 17h, write stops and “0” data is output as the read data.
SI
CSB
SCK
CSB
SCK
SO
SO
SI
SI
R/W; “0”: Write, “1”: Read
R/W
= 0
= 1
R/W
R/W
Hi-Z
Hi-Z
0
0
0
0
0
0
A4
A4
Figure 14.3 Current Address Access Mode Output Timing Chart
Figure 14.2 Current Address Access Mode Input Timing Chart
A4
Address: “n”
Address: “n”
1
A3
A3
st
byte
A2
A2
A3
A1
A1
A2
A[4:0]; Register address
A0
A0
Figure 14.1 SI Input Data Format
MSB
MSB
D7
D7
A1
D6
D6
LC89075W-H
A0
D5
D5
Data of “n”
Data of “n”
D4
D4
Control data
D3
D3
2
nd
byte
D2
D2
D1
D1
LSB MSB
LSB MSB
D0
D0
Control data; 8 bits data [MSB:LSB]
D7
D7
Control data
Data of “n+1”
Data of “n+1”
3
rd
byte
D1
D1
LSB MSB
LSB MSB
D0
D0
D7
D7
Control data
Data of “n+2”
Data of “n+2”
n byte
D1
D1
No.A1858-42/69
LSB
LSB
D0
D0