BT8222EPFF CONEXANT [Conexant Systems, Inc], BT8222EPFF Datasheet - Page 102

• Manufacturer Part Number: BT8222EPFF
• Description: ATM Transmitter/Receiver with UTOPIA Interface
• Manufacturer: CONEXANT [Conexant Systems, Inc]

3.0 Registers
3.4 Transmit Control Registers
0x04–0x07—CELL_GEN_x (Cell Generation Control Registers)
The CELL_GEN_x registers are located at addresses 0x04–0x07. Each of the four FIFO ports has its own ATM
Cell Generation Control Register, so x is 0, 1, 2 or 3. Cell generation is described in detail in
description of CELL_GEN_x Control Register addresses is provided in
Table 3-7. CELL_GEN_x Control Register Addresses
3-16
15, 14
13
12
11
10
9
8
7
6
5
4
3, 2
1, 0
0x04
0x05
0x06
0x07
Bit
Address
2
1
1
1
1
1
1
1
1
1
1
2
2
Field
Size
CELL_GEN_0
CELL_GEN_1
CELL_GEN_2
CELL_GEN_3
Reserved
Inhibit Single Cell
Generation
Error Payload CRC
Error HEC
Disable Payload
CRC
Disable HEC
Insert CLP
Insert PT
Insert VCI
Insert VPI
Insert GFC
Port Priority
Cell Generation
Mode
Name
Register Name
Set to 0.
Inhibits cell transmission from the port for a single cell period and inserts an idle
cell in its place.
Forces an error in the payload CRC-10 field. A single error is generated; then this
bit is cleared.
Forces an error in the ATM header HEC field. A single error is generated; then this
bit is cleared.
Disables payload CRC-10 field generation and allows the existing field from the
FIFO input to pass.
Disables the ATM header HEC field (octet 5) generation and allows the existing field
from the FIFO input to pass. The error mask in the TXFEAC_ERRPAT register
controls which bits are errored in the HEC field by XOR’ing this mask with the
calculated HEC, allowing the microprocessor to generate a specific number of
errors.
Performs the same insertion function as Insert GFC (bit 4) for the CLP bit.
Performs the same insertion function as Insert GFC (bit 4) for the 3-bit payload
type field.
Performs the same insertion function as Insert GFC (bit 4) for the 16-bit VCI field.
Performs the same function as the Insert GFC (bit 4) for the 8-bit VPI field.
Allows the 4-bit GFC field obtained from the FIFO interface to be overwritten with
the value programmed in the corresponding TX_HDR registers [0x0C–0x13]. This
bit is only valid in 52-, 53-, and 57-octet modes. In 48-octet mode, the GFC field is
always taken from the TX_HDR register.
Allows the cell generator to assign four priority levels to the transmit source.
Selects the mode of operation for the generation circuit.
0 0 48 octet
0 1 52 octet
1 0 53 octet
1 1 57 octet
Conexant
Cell Generation Control—Port 0 + UTOPIA
Cell Generation Control—Port 1
Cell Generation Control—Port 2
Cell Generation Control—Port 3
ATM Transmitter/Receiver with UTOPIA Interface
Description
Table
Description
3-7.
Section
2.6. A
CN8223
100046C