CN8330EPD CONEXANT [Conexant Systems, Inc], CN8330EPD Datasheet

CN8330EPD

Manufacturer Part Number

CN8330EPD

Description

DS3/E3 Framer with 52 Mbps HDLC Controller

Manufacturer

CONEXANT [Conexant Systems, Inc]

Datasheet

1.CN8330EPD.pdf (101 pages)

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Data Sheet

CN8330

DS3/E3 Framer with 52 Mbps HDLC Controller

The CN8330 is an integral DS3/E3 framer designed to support the transmission

formats defined by ANSI T1.107-1988, T1.107a-1989, T1.404, and ITU-T G.751

standards. All maintenance features required by Bellcore TR-TSY-000009 and AT&T

PUB 54014 are provided. In addition, the CN8330 can be optionally configured as a

High-Level Data Link Controller (HDLC) usable with or without DS3/E3 framing

overhead.

E3 formatted signals. A First In First Out (FIFO) buffer in the receive path can be

enabled to reduce jitter on the incoming data. Transmit and receive data is available to

the host in either serial or parallel byte and nibble formats. Access is provided to the

terminal data link and the Far End Alarm/Control (FEAC) channel, as specified in

T1.107a-1989. Counters are included for frame-bit errors, Line Code Violations

(LCVs), parity errors, and Far End Block Errors (FEBEs).

control modes. The microprocessor control mode monitors all status conditions and

provides configuration control. The stand-alone monitor mode allows the CN8330 to

operate as a monitor providing status and alarm information on external pins.

Functional Block Diagram

RXNEG

DS3CKI

RXPOS

TXNEG

TXPOS

TCLKO

AD[7:0]

Control

TXCKI

The CN8330 provides framing recovery for M13, C-bit parity, Syntran, and G.751

Two operational modes are available: microprocessor and stand-alone monitor

Microprocessor

Loopback

Source

Line

Interface

Conversion

Encoder

Unipolar

Bipolar

To/From

All Blocks

Overhead

Framing/

Insertion

Bypass

Enable

FIFO

Processing

Transmitter

Overhead/

Processing

Recovery

Data Link

Overhead/

Data Link

Framing

Receiver

PPDL

RXMSY

CBITO

RXCCK

RXDAT

RXCLK

Status

TXBCK

TDAT[7:0]

TXCCK

CBITI

RDAT[7:0]

RXBCK

Status

TXCKI

TXDATI

TXSYI

Distinguishing Features

• Supports DS3/E3 framing modes

• Includes high-speed HDLC controller

• Framing recovery for M13, C-bit

• Serial or parallel (octet or nibble)

• Average reframe time of less than

• Supports the LAPD terminal data link

• 68-pin PLCC or 80-pin MQFP

• Operates from a single +5 VDC ±5%

• Low-power CMOS technology

Applications

• Digital PCM switches

• Digital Cross-Connect Systems

• Channel Service Units (CSUs)

• Channel extenders

• ATM Switches/Concentrators

• PBXs

• Switched Multimegabit Digital

• Test equipment

• Routers (including HSSI ports)

(52 MHz)

parity, Syntran, and G.751 E3 signals

interface modes

1 ms for DS3 and less than 250 µs

for E3

and FEAC channel as defined in

T1.107a-1989

surface-mount package

power supply

Service (SMDS) Equipment

October 13, 1999

100441E

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