BT8375 CONEXANT [Conexant Systems, Inc], BT8375 Datasheet - Page 220

• Manufacturer Part Number: BT8375
• Description: single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces
• Manufacturer: CONEXANT [Conexant Systems, Inc]

3.16 Data Link Registers
DL2_BIT[7:0]
TDL2_RPT
DL2[1: 0]
3-102
0B0—DL2 Bit Enable (DL2_BIT)
0B1—DL2 Control (DL2_CTL)
DL2_BIT[7]
—
7
7
DL2_BIT[6]
NOTE:
DL2 Bit Select—Works in conjunction with DL2_TS [addr 0AF] to select 1 or more time slot
bits for data link input and output. Any combination of bits can be enabled by writing the
corresponding DL2_BIT active (high). Where the LSB enables first bit transmitted or received,
and MSB enables eighth bit transmitted or received, DL2_BIT has no effect when DL2_TS
selects T1 F-bits.
NOTE:
The Circular Buffer/FIFO control bit [TDL2_RPT; addr 0B1] allows the FIFO to act as a
circular buffer; in this mode, a message can be transmitted repeatedly. This feature is available
only for unformatted transmit data link applications. The processor can repeatedly send fixed
patterns on the selected channel by writing a 1- to 64-byte message into the circular buffer. The
programmed message length repeats until the processor writes a new message. The first byte of
each unformatted message is output automatically, aligned to the first frame of a 24-, or
16-frame transmit multiframe (SF/ESF/MFAS). This allows the processor to source overhead
or data elements aligned to the TX timebase. In both SF and ESF T1 modes, unformatted
messages are aligned on 24-frame boundaries. Therefore, in SF applications, the repeating
message must be designed to span two SF multiframes. Each unformatted message written is
output-aligned only after the preceding message completes transmission. Therefore, data
continuity is retained during the linkage of consecutive messages, provided that the content of
each message consists of a multiple of the multiframe length.
Data Link 2 mode—Selects either HDLC formatted (FCS or non-FCS) transmit and receive
data link message mode or unformatted (Pack8 or Pack6) message mode. During HDLC
modes, the transmit/receive circuits perform zero insertion/removal after each occurrence of
five consecutive 1s contained in the message bits, FLAG (0x7E) character insertion/removal
during idle channel conditions, and ABORT (0xFF) code insertion/detection, upon errored
channel conditions. Refer to ITU-T Recommendation Q.921 for complete details of the HDLC
link-layer protocol. FCS mode automatically generates, inserts, and checks the 16-bit FCS
without passing FCS bits through transmit and receive FIFOs. Non-FCS mode passes all
message bits that exist between the opening and closing FLAG characters through the FIFOs
without generating or checking FCS bits. Non-FCS mode allows the processor to generate and
check the entire contents of each HDLC frame.
—
6
6
Not available in Bt8376 device.
Not available in Bt8376 device.
DL2_BIT[5]
—
5
5
0 = disable data link bit
1 = enable data link bit
DL2_BIT[4]
TDL2_RPT
4
4
Conexant
DL2_BIT[3]
DL2[1]
3
3
Fully Integrated T1/E1 Framer and Line Interface
DL2_BIT[2]
DL2[0]
2
2
DL2_BIT[1]
TDL2_EN
Bt8370/8375/8376
1
1
DL2_BIT[0]
N8370DSE
RDL2_EN
0
0