BT8375 CONEXANT [Conexant Systems, Inc], BT8375 Datasheet - Page 232

• Manufacturer Part Number: BT8375
• Description: single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces
• Manufacturer: CONEXANT [Conexant Systems, Inc]

3.17 System Bus Registers
BUS_RSB
SIG_OFF
RPCM_NEG
RSYN_NEG
BUS_FRZ
RSB_CTR
3-114
0D1—Receive System Bus Configuration (RSB_CR)
BUS_RSB
7
Enable Bussed RSB Outputs—Applicable only if the system bus outputs are controlled by SBI
timebases [SBI_OE = 1; addr 0D0]. When BUS_RSB is active, RPCMO, RSIGO, and RINDO
outputs from multiple devices are allowed to share common receive system bus connections.
Unused time slots are three-stated during those bus groups not selected by SBI mode [addr
0D0]; otherwise, unused time slots repeat their output data value for all bus groups.
Inhibit RPCMO Signaling Reinsertion—Disables insertion of ABCD signaling for all time
slots on the receive system bus PCM output (RPCMO); otherwise, ABCD signaling is
reinserted on RPCMO, as controlled by System Bus Per-Channel [SBCn; addr 0E0–0FF] and
RX Per-Channel [RPCn; addr 180–19F] controls.
Output Data on Falling Edge Clock—Selects RSBCKI rising or falling edge clock signal to
output RPCMO, RSIGO, RINDO, and SIGFRZ.
Output Sync on Falling Edge Clock—Selects RSBCKI rising or falling edge clock signal for
RFSYNC or RMSYNC outputs. Opposite RSBCKI edge is used if RFSYNC or RMSYNC is
programmed as input.
RFSYNC or RMSYNC must be sampled low during the previous falling clock edge, then
sampled high at the rising clock edge. (Refer to
for RFSYNC/RMSYNC and TFSYNC/TMSYNC Input Signals
and Hold
Enable Bused SIGFRZ Output—Enables SIGFRZ from multiple devices to share a common
receive system bus connection. When active, SIGFRZ three-states during bus group time slots
unused by the selected SBI mode [addr 0D0].
Force RSLIP to Center—Writing a one to RSB_CTR forces RSLIP read buffer pointer to its
initial delay condition. If RFSYNC or RMSYNC is programmed as an output, RSB_CTR
forces a change of system bus sync alignment. The processor must assert RSB_CTR after
configuration of the receive slip buffer. Centering RSLIP does not effect RSLIP status reported
in ISR.5 [addr 006]. RSB_CTR must be written to a 1, then to a 0. This bit is not self-clearing.
SIG_OFF
When RFSYNC or RMSYNC is an input and configured for rising edge sampling,
6
Timing.)
RPCM_NEG
5
0 = RSB time slot value repeated for all bus groups
1 = three-state RSB outputs during unused bus groups
0 = enable insertion of signaling onto RPCMO
1 = inhibit RPCMO signaling
0 = RSB rising edge outputs
1 = RSB falling edge outputs
0 = RFSYNC or RMSYNC rising edge output (falling edge input)
1 = RFSYNC or RMSYNC falling edge output (rising edge input)
0 = SIGFRZ repeats for all bus groups
1 = three-state SIGFRZ during unused bus groups
0 = no effect
1 = force RSLIP to center
RSYN_NEG
4
Conexant
BUS_FRZ
3
Fully Integrated T1/E1 Framer and Line Interface
Figure 5-5, SBI Timing: Setup and Hold Time
RSB_CTR
2
and
Table 5-6, Input Data Setup
RSBI[1]
Bt8370/8375/8376
1
N8370DSE
RSBI[0]
0