P4C1048L PYRAMID [Pyramid Semiconductor Corporation], P4C1048L Datasheet - Page 7

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P4C1048L

Manufacturer Part Number
P4C1048L
Description
LOW POWER 512K x 8 CMOS STATIC RAM
Manufacturer
PYRAMID [Pyramid Semiconductor Corporation]
Datasheet
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE
AC TEST CONDITIONS
* including scope and test fixture.
Note:
Because of the high speed of the P4C1048L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the V
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between V
Document # SRAM129 REV D
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
Input Pulse Levels
Figure 1. Output Load
CC
and ground.
See Fig. 1 and 2
CC
GND to 3.0V
and ground planes
1.5V
1.5V
3ns
CE
CE CONTROLLED)
CE
CE
To avoid signal reflections, proper termination must be used; for example,
a 50 test environment should be terminated into a 50 load with 1.77V
(Thevenin Voltage) at the comparator input, and a 589 resistor must be
used in series with D
TRUTH TABLE
D
OUT
Standby
Mode
Read
Write
Disabled
Figure 2. Thevenin Equivalent
CE
CE
CE
CE
CE
OUT
H
L
L
L
to match 639
OE
OE
OE
OE
OE
H
X
X
L
(6)
WE
WE
WE
WE
WE
H
X
H
L
(Thevenin Resistance).
High Z
High Z
D
I/O
D
OUT
IN
Page 7 of 12
Standby
Power
Active
Active
Active
P4C1048L

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