EM6580SO14A EMMICRO [EM Microelectronic - MARIN SA], EM6580SO14A Datasheet - Page 18

• Manufacturer Part Number: EM6580SO14A
• Description: Ultra Low Power 8-pin Flash Microcontroller
• Manufacturer: EMMICRO [EM Microelectronic - MARIN SA]

6.2.4 Software test variables
As shown in Figure 10 PA[0/5] or PA[3/4] are also used as input conditions for conditional software branches.
These CPU inputs are always debounced and non-inverted.
CPU TestVar3 is connected to Ground and can not be used in Software.
6.2.5 Port A for 10-Bit Counter
The PA[1] and PA[3/4] inputs can be used as the clock input terminal for the 10 bit counter
6.2.6 Port A Wake-Up on change
In sleep mode if configured port PA[0/5] or PA[3/4] inputs are continuously monitored to wake up on change,
which will immediately wake up the EM6580.
6.2.7 Port A for Serial Interface
When the serial interface is used in slave mode, PA[0] is used for serial data input and PA[1] for the serial
clock.
6.2.8 Port A for External Reset
In Active and Stand-by (Halt) mode a positive debounced pulse on PA[3/4] can be the source of a reset when
PA[3/4]ResIn and InResAH are set at ‘1’. When IrqPA[3l/4h] is ‘0’ than PA[3] is selected for Reset source
and when IrqPA[3l/4h] is ‘1’ than PA[4] is selected for Reset source.
6.2.9 Port PA[4] as Comparator Input
When using the PA[4] as an input to the internal SVLD comparator NO pull resistor should be connected on
this terminal. Otherwise the device may draw excessive current.
First PA[4] pull-up/down resistor should be disconnected by software and the ExtVcheck bit can be set to ‘1’.
This dedicates PA[4] as SVLD resistor divider input to the SVLD comparator.
At this point the measurements respect the same timing as any other SVLD measurements as explained in
Chapter Supply Voltage Detector. It can also generate an IRQ if the input voltage is lower as Comparator level.
Thus configured a direct read of PA[4] will result in reading ‘0’.
6.2.10 Reset and Sleep on Port A
During circuit initialisation, all Control registers are reset by Power On Reset and therefore all pull-ups are off
and all pull-downs are on.
During Sleep mode, the circuit retains its register values. As such the PA configurations remain active also
during Sleep.Sleep mode is cancelled with any Reset. However the Reset State does not reset the Control
registers bits which are specifically marked to be initialised by POR only. (Pull, Nch Open drain, Freq out, etc
configurations).
however Sleep mode is cancelled with a Reset and all system register will be reinitialized at this point. (the
circuit is in Reset State. and pull-downs, if previously turned on. After any reset the serial interface parameters
are reset to : Slave mode, Start and Status = 0, LSB first, negative edge shift , PA[3:0] tri-state.
6.2.11 Port A Blocked Inputs
In sleep mode if PortA inputs are not used and prepared for Wake-Up on Change or Reset these inputs are
blocked. At that time port can be undefined from external and this will not generate an over-consumption.
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
Copyright © 2006, EM Microelectronic-Marin SA
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debounced PA[0/5] is connected to CPU TestVar1
debounced PA[3/4] is connected to CPU TestVar2
PA[1] is at counter clock selection 0. The input is direct ( no debouncer is possible
PA[3/4] is at counter clock selection 7. As for the IRQ generation, debounced or input directly and
non-inverted or inverted input is possible. This is defined with the register RegPaCntl1. Debouncing
the input is always recommended.
: Blocked if Sleep bit set and no IRQ or Wake-up defined on this input
: Blocked if Sleep bit set
: Blocked if Sleep bit set
: Blocked if Sleep bit set and no IRQ or Wake-up defined on this input
: Blocked if Sleep bit set and no IRQ or Wake-up defined on this input
: Never blocked
Also blocked if External VLD check enabled
R
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