EM6580SO14A EMMICRO [EM Microelectronic - MARIN SA], EM6580SO14A Datasheet - Page 28

• Manufacturer Part Number: EM6580SO14A
• Description: Ultra Low Power 8-pin Flash Microcontroller
• Manufacturer: EMMICRO [EM Microelectronic - MARIN SA]

8.2 Frequency Select and Up/Down Counting
Eight (8) different input clocks can be selected to drive the Counter. The selection is done with bits
CountFSel2…0 in register RegCCntl1. Six (6) of this input clocks are coming from the prescaler. The
maximum prescaler clock frequency for the counter is half the system clock SysClk and the lowest is 1Hz typ.
Therefore a complete counter roll over can take as much as 17.07 minutes (1Hz clock, 10 bit length) or as little
as 977 μs (Ck[15] typ 16.3kHz, 4 bit length). The IRQCount0, generated at each roll over, can be used for time
bases, measurements length definitions, input polling, wake up from Halt mode, etc. The IRQCount0 and
IRQComp are generated with the system clock Ck[16] rising edge. IRQCount0 condition in up count mode is :
reaching 3FF if 10-bit counter length (or FF, 3F, F in 8, 6, 4-bit counter length). In down count mode the
condition is reaching ‘0’. The non-selected bits are ‘don’t care’. For IRQComp refer to section 8.4.
Note: The Prescaler and the Microprocessor clock’s are usually non-synchronous, therefore time bases
generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down
mode). However the prescaler clock can be synchronized with µP commands using for instance the prescaler
reset function.
Figure 17. Counter Clock Timing
The two remaining clock sources are coming from the PA[1] or PA[3/4] terminals. Refer to Figure 10 on page
15 for details. Input PA[1] can be only direct non-debounce input, second PA[3/4] can be either debounce
(Ck[11] or Ck[8]) or direct input, the input polarity can also be chosen. The outputs for Timer clock inputs are
named TimCk0 and TimCk7 respectively. For the debouncer and input polarity selection refer to chapter 6.
In the case of port A input clock without debouncer, the counting clock frequency will be half the input clock on
port A. The counter advances on every odd numbered port A negative edge ( divided clock is high level ).
IRQCount0 and IRQComp will be generated on the rising PA[3/4] or PA[1] input clock edge. In this condition
the EM6580 is able to count with a higher clock rate as the internal system clock (Hi-Frequency Input).
Maximum port A input frequency is limited to 500kHz (@V
contact EM Microelectronic’s.
In both, up or down count (default) mode, the counter is cyclic. The counting direction is chosen in register
RegCCntl1 bit Up/Down (default ‘0’ is down count). The counter increases or decreases its value with each
positive clock edge of the selected input clock source. Start up synchronization is necessary because one can
not always know the clock status when enabling the counter. With EvCount=0, the counter will only start on the
next positive clock edge after a previously latched negative edge, while the Start bit was already set to ‘1’. This
synchronization is done differently if event count mode (bit EvCount) is chosen. Refer also to
Internal Clock Synchronization.
Copyright © 2006, EM Microelectronic-Marin SA
Prescaler Clock
Counter IRQ’s
Counter IRQ’s
System Clock
System Clock
Divided Clock
Port A Clock
Counting
Counting
R
Prescaler Frequencies or Debounced Port A Clocks
Non Debounced Port A Clocks (System Clock Independent)
dd
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≥ 1.5 V). If higher frequencies are needed, please
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EM6580
F igure 18.
1 0 3 H