EM6580SO14A EMMICRO [EM Microelectronic - MARIN SA], EM6580SO14A Datasheet - Page 23

• Manufacturer Part Number: EM6580SO14A
• Description: Ultra Low Power 8-pin Flash Microcontroller
• Manufacturer: EMMICRO [EM Microelectronic - MARIN SA]

7.1 General Functional Description
After power on or after any reset the serial interface is in serial slave mode with Start and Status set to 0, LSB
first, negative shift edge and all outputs are in high impedance state.
When the Start bit is set, the shift operation is enabled and the serial interface is ready to transmit or receive
data, eight shift operations are performed: 8 serial data values are read from the data input terminal into the
shift register and the previous loaded 8-bits are send out via the data output terminal. After the eight shift
operation, an interrupt is generated, and the Start bit is reset.
Parallel to serial conversion procedure ( master mode example ).
Serial to parallel conversion procedure (slave mode example).
7.2 Detailed Functional Description
Master or Slave mode is selected in the control register RegSCntl1.
In Slave mode, the serial clock comes from an external device and is input via the PA[1] terminal as a
synchronous clock (SCLKIn) to the serial interface. The serial clock is ignored as long as the Start bit is not
set. After setting Start, only the eight following active edges of the serial clock input PA[1] are used to shift the
serial data in and out. After eight serial clock edges the Start bit is reset. The PA[3] terminal is a copy of the
(Start OR Status) bit values, it can be used to indicate to the external master, that the interface is ready to
operate or it can be used as a chip select signal in case of an external slave.
In Master mode, the synchronous serial clock is generated internally from the system clock. The frequency is
selected from one out of three sources ( MS0 and MS1 bits in RegSCntl1) . The serial shifting clock is only
generated during Start = high and is output to the SCLK terminal as the Master Clock (SCLKOut). When Start
is low, the serial clock output on PA[1] is 0.
An interrupt request IRQSerial is generated after the eight shift operations are done. This signal is set by the
last negative edge of the serial interface clock on PA[1] (master or slave mode) and is reset to 0 by the next
write of Start or by any reset. This interrupt can be masked with register RegIRQMask2. For more details
about the interrupt handling see chapter 11.
Serial data input on PA[0] is sampled by the positive or negative serial shifting clock edge, as selected by the
Control Register POSnNeg bit. Serial data input is shifted in LSB first or MSB first, as selected by the Control
Register MSBnLSB bit.
Copyright © 2006, EM Microelectronic-Marin SA
Setup the circuit IO’s accordingly.
Write to RegSCntl1 serial control (clock freq. in master mode, edge and MSB/LSB select).
Write to RegSDataL and RegSDataH (shift out data values).
Write to RegSCntl2 (Start=1, mode select, status).
After the eighth clock an interrupt is generated, Start becomes low. Then, interrupt handling
Setup the circuit IO’s accordingly.
Write to RegSCntl1 (slave mode, edge and MSB/LSB select).
Write to RegSCntl2 (Start=1, mode select, status).
After eight serial clocks an interrupt is generated, Start becomes low.
Interrupt handling.
Shift register RegSDataL and RegSDataH read.
A new shift operation can be authorized.
R
23
Starts the shift out
www.emmicroelectronic.com
EM6580