EM6580SO14A EMMICRO [EM Microelectronic - MARIN SA], EM6580SO14A Datasheet - Page 20

• Manufacturer Part Number: EM6580SO14A
• Description: Ultra Low Power 8-pin Flash Microcontroller
• Manufacturer: EMMICRO [EM Microelectronic - MARIN SA]

6.4 Port A registers
The two Control registers for Input control, RegPACntl1 and RegPACntl2, were already shown in chapter
Input / Output Ports Overview.
Table 6.4.1 Register RegPA0
Table 6.4.2 Register RegPa0OE
Table 6.4.3 Register Pa0noPDown
Table 6.4.4 Register Pa0NchOpenDr
Table 6.4.5 Register RegPA1
Table 6.4.6 Register RegFreqRst
Interrupt PortA Control bits MaskIRQPA[0/5] and MaskIRQPA[3/4] used to enable (Mask) the Interrupt
ReQuest IRQ from PortA are in register RegIRQMask1.
Interrupt status bits IRQPA[0/5] and IRQPA[3/4] used to signal the Interrupt from PortA are in register
RegIRQ1. They are both shown in Chapter Interrupt Controller.
Note: CPUClk = RCClk if no external clock used.
Copyright © 2006, EM Microelectronic-Marin SA
Bit
Bit
Bit
Bit
Bit
Bit
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
In case of external clock, CPUClk is equal to the PA[1] input clock.
* Direct read on Port A terminals
POR* Reset only with Power On Reset
* Reset only with Power On Reset, Default "0" is: CMOS on PA[3..0]
* Direct read on Port A terminals
NchOpDrPA[3]
NchOpDrPA[2]
NchOpDrPA[1]
NchOpDrPA[0]
NchOpDrPA[5]
P** On Reset PA[2] is forced to output if ( PA[0]=’0’, PA[1]=’1’, PA[4]=’1’, Sout/RstPA[2]=’1’ and
freqOutPA[2]=’1’ ) until System reset is finished. Refer also to
After Reset is finished and circuit starts to execute instructions PA[2] becomes tri-state input.
Bit OEnPA[2] is reset to ‘0’ with every Reset.
NoPdPA[3]
NoPdPA[2]
NoPdPA[1]
NoPdPA[0]
PAData[4]*
PA3/4resIn
R
PAData[3]
PAData[2]
PAData[1]
PAData[0]
PAData[5]
OEnPA[3]
OEnPA[2]
OEnPA[1]
OEnPA[0]
OEnPA[5]
foutSel[1]
foutSel[0]
InResAH
Name
Name
Name
Name
Name
Name
Reset
Reset
Reset
POR*
POR*
0 P**
POR
p**
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
p
p
x
x
R* /W
R* /W
R* /W
R* /W
R* /W
R* /W
R* /W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R*
p** reset to ‘0’ by POR only
I/O control for PA[3] , output when OEnPA[3] = Hi
I/O control for PA[2] , output when OEnPA[2] = Hi
I/O control for PA[1] , output when OEnPA[1] = Hi
I/O control for PA[0] , output when OEnPA[0] = Hi
I/O control for PA[5] , output when OEnPA[5] = Hi
PA3/4 dedicated for Input reset when set at ‘1’
(11)CPUClk, (10) SysClk, (01) 2kHz, (00) 1Hz
Input reset On in Active and StandBy mode
Output Frequency selection (foutSel[1:0])
20
PA[3] input and PAout[3] output
PA[2] input and PAout[2] output
PA[1] input and PAout[1] output
PA[0] input and PAout[0] output
PA[5] input and PAout[5] output
Nch. Open Drain on PA[3]
Nch. Open Drain on PA[2]
Nch. Open Drain on PA[1]
Nch. Open Drain on PA[0]
Nch. Open Drain on PA[5]
No pull-down on PA[3]
No pull-down on PA[2]
No pull-down on PA[1]
No pull-down on PA[0]
T able 6.4.11.
1 0 1 H
Description
Description
Description
Description
Description
Description
PA[4] input
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6 ;
1 0 0 H