ZR36067PQC ETC [List of Unclassifed Manufacturers], ZR36067PQC Datasheet - Page 27

• Manufacturer Part Number: ZR36067PQC
• Description: AV PCI CONTROLLER
• Manufacturer: ETC [List of Unclassifed Manufacturers]

13.4 Video Display “Top” Register
This register contains the doubleword base address of the top
field.
Address Offset: 0x00C
13.5 Video Display “Bottom” Register
This register contains the doubleword base address of the
bottom field.
Address Offset: 0x010
13.6 Video Stride, Status and Frame Grab Register
This register contains parameters for display addressing (bytes
2-3), status of VFIFO (byte 1) and frame grab control (byte 0).
Address Offset: 0x014
31:18
17:16
31:2
31:2
15:9
Bit
1:0
Bit
1:0
Bit
7:2
8
Type
Type
Type
RW
RW
RW
RC
R
R
R
R
R
Mod
Mod
Mod
vid
vid
vid
all
VidTopBase - Video Top Field Base
Address. This is the destination starting
address for the top field.
Default value is 0xFFFFFFFC.
Bits 1..0 are hardwired to 00b.
VidBotBase - Video Bottom Field Base
Address.
This is the destination starting address for the
bottom field.
Default value is 0xFFFFFFFC.
Bits 1..0 are hardwired to 00b.
DispStride - Display Stride.
This register defines the address increment in
bytes to be added to the address of the last
pixel of a display line, to generate the address
of the next consecutive display line.
If the address difference between two con-
secutive display lines is zero (i.e, they are
physically consecutive) than DispStride
should be set (by the driver software) to zero
(if DispMode=1) or to the display line size in
bytes (if DispMode=0).
Default value is 0xFFFC.
Bits 1..0 are hardwired to 00b.
Reserved. Returns zero.
VidOvf - Video FIFO Overflow flag.
This bit is asserted by the Video FIFO server
when an overflow of the Video FIFO occurs.
This bit is cleared when the host tries to write
‘1’ to it.
In case of concurrent accesses to this bit, it
remains ‘1’.
‘1’ - a VFIFO overflow occurred.
‘0’ - no overflow (default value).
Reserved. Returns zero.
Description
Description
Description
27
Address Offset: 0x014
13.7 Video Display Configuration Register
This register contains the configuration parameters for the video
display.
Address Offset: 0x018
30:24
Bit
Bit
31
24
1
0
Type
Type
RW
RW
RW
RW
RS
snap
Mod
Mod
vid
vid
all
all
SnapShot - Frame Grab Mode.
If this bit is asserted the ZR36067 goes into
frame grab mode. When deasserted continu-
ous display of video is resumed.
‘1’ - frame grab mode.
‘0’ - continuous display mode (default value).
FrameGrab - Frame Grabbing Command/
Status.
When this bit is asserted by the host and
SnapShot is asserted, the ZR36067 will
transfer the next two fields (indicated by the
VSYNC signal) to memory. At the end of the
second field this bit will be cleared internally,
indicating that the frame grabbing has been
completed and video transfer has been
stopped.
In case of concurrent accesses to this bit, the
result is ‘0’.
‘1’ - start frame grabbing.
‘0’ - frame grabbing completed (default
value).
Description
VidEn - Video Display Enable.
If this bit is cleared by the host, video write
DMA transfers are disabled. When enabled,
the video DMA controller operates normally.
‘1’ - normal video transfer mode.
‘0’ - video write transfers disabled (default
value).
MinPix - Minimum Number of doublewords.
This parameter defines a threshold value.
When the number of doublewords inside the
Video FIFO has reached this value a video-
write burst is requested.
Default value is 0x0F.
Range 0x01 - 0x3C.
The l.s. bit of this field (bit 24) is also used to
configure the platform PCI bridge type, so the
actual resolution of MinPix is limited by the
Triton bit. When the Triton bit is ‘1’, only odd
values of MinPix are supported. When the
Triton bit is ‘0’, only even values are
supported.
Triton - PCI Bridge Controller type.
This parameter configures the PCI REQ
behavior to match the platform PCI bridge
characteristics.
‘0’ - Intel ‘Triton’ Bridge Controller. The REQ
assertion and de-assertion conditions are
modified accordingly.
‘1’ - Other PCI Bridge Controllers.
Default value is ‘1’.
This bit is also used as the l.s. bit of MinPix.
AV PCI CONTROLLER
Description