ZR36067PQC ETC [List of Unclassifed Manufacturers], ZR36067PQC Datasheet - Page 7

• Manufacturer Part Number: ZR36067PQC
• Description: AV PCI CONTROLLER
• Manufacturer: ETC [List of Unclassifed Manufacturers]

3.0 PIN DESCRIPTIONS
PCI Interface (48 pins)
AD[31:0]
C/BE[3:0]
PAR
FRAME
TRDY
IRDY
STOP
DEVSEL
IDSEL
REQ
GNT
PCICLK
PCIRST
INTA
Digital Video Bus Interface (32 pins)
Y[7:0]/R[7:0]
UV[7:0]/G[7:0]
B[7:0]
VCLKx2
VCLK
HSYNC
VSYNC
FI
PXEN
RTBSY
START
GuestBus Interface (25 pins)
GCS[7:0]
GADR[2:0]
GDAT[7:0]
GRD
GWR
GRDY
GWS
GIRQ[1:0]
CodecBus Interface (11 pins)
CODE[7:0]
CEND
CCS
CBUSY
I2C Bus Interface (2 pins)
SDA
Symbol
open drain
Type
3-state*
3-state*
3-state*
3-state*
3-state*
3-state
3-state
3-state
3-state
3-state
3-state
3-state
3-state
3-state
3-state
3-state
3-state
OD
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
[1]
Direction
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Multiplexed address and data bus pins.
Bus commands or byte enables.
Even parity bit for AD31..0 and C/BE[3:0].
PCI cycle frame.
PCI target ready indicator.
PCI initiator ready.
Indicates a target request to stop the current data transfer.
PCI device select, indicates that the target has decoded its address.
PCI initialization device select. Used as a chip-select to the ZR36067’s configuration space.
PCI bus request.
PCI bus grant.
PCI clock.
PCI reset. When active, all ZR36067 output pins are tri-stated. A low to high transition puts the
ZR36067 into its power-on reset state. Minimum active low duration is 3 PCI clocks.
PCI interrupt request A. A low level on this signal requests an interrupt from the host.
Luminance/Red video lines. Also used to program the low byte of Subsystem Vendor ID.
Chrominance/Green video lines. Also used to program the low byte of Subsystem ID.
Blue video lines.
Double frequency video bus clock.
Digital video bus clock. Used as a qualifier to VCLKx2. Must be synchronized to VCLKx2.
Digital video bus horizontal sync.
Digital video bus vertical sync.
Digital video bus field indicator (top/bottom).
Active low Pixel Enable output to the ZR36016.
Active low Strip Memory Overflow/Underflow signal from the ZR36016.
Active high Start process output to the ZR36016.
Active low chip-select output to guest bus devices.
Address outputs to guest bus devices.
Guest data bus. Also used to program the high byte of Subsystem Vendor ID.
Active low read output to guest bus devices.
Active low write output to guest bus devices.
Active high “guest ready” input, used only in MPEG code-DMA mode as a data request.
Guest Wait-State indication. Assertion of this active-low input allows the guest device to extend
the GuestBus write (or read) cycle until it is capable of latching-in (or providing) the data.
Positive-edge-sensitive interrupt request inputs from one or two of the guest bus slave devices.
Code Bus connected to the ZR36050.
Active low End of field process indication from the ZR36050.
Active low Code Bus active cycle signal from the ZR36050.
Active low Code FIFO Busy indication to the ZR36050.
I
2
C bus data
7
Description
AV PCI CONTROLLER