K9F6408Q0C-H SAMSUNG [Samsung semiconductor], K9F6408Q0C-H Datasheet
K9F6408Q0C-H
Related parts for K9F6408Q0C-H
K9F6408Q0C-H Summary of contents
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... The min. Vcc value 1.8V devices is changed. 0.5 K9F64XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V 0.6 Pb-free Package is added. K9F6408U0C-QCB0,QIB0 K9F6408U0C-HCB0,HIB0 K9F6408Q0C-HCB0,HIB0 K9F6408U0C-FCB0,FIB0 0.7 Note is added. (VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations less.) 0.8 1. Add the Protrusion/Burr value in WSOP1 PKG Diagram. ...
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... Ball TBGA ( 6 x 8.5 /0.8mm pitch , Width 1.0 mm) - K9F6408U0C-VCB0/VIB0 48 - Pin WSOP I (12X17X0.7mm) - K9F6408U0C-QCB0/QIB0 : Pb-free Package 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch) - K9F6408Q0C-HCB0/HIB0 : Pb-free Package 48- Ball TBGA ( 6 x 8.5 /0.8mm pitch , Width 1.0 mm) - K9F6408U0C-FCB0/FIB0 : Pb-free Package 48 - Pin WSOP I (12X17X0.7mm) * K9F6408U0C-V,F(WSOPI ) is the same device as K9F6408U0C-T,Q(TSOPII) except package type. ...
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... K9F6408Q0C K9F6408U0C PIN CONFIGURATION (TSOP II ) K9F6408U0C-TCB0,QCB0/TIB0,QIB0 PACKAGE DIMENSIONS 44(40) LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP II - 400F #44(40) #1 18.81 Max. 0.741 18.41 0.10 0.725 0.004 0.805 0.35 0.10 0.032 0.014 0.004 CLE ALE R GND N N.C N N.C N N.C N ...
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... K9F6408Q0C K9F6408U0C PIN CONFIGURATION (TBGA) K9F6408X0C-BCB0,HCB0/BIB0,HIB0 PACKAGE DIMENSIONS 48-Ball TBGA (measured in millimeters) Top View 6.00 0.10 Ball # N.C WP ALE CE WE R/B N.C RE N.C N.C N.C CLE N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O N.C N.C N N.C V I/O N.C I/O I/O CCQ I/O I/O I/O I (Top View) (Datum (Datum ...
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... K9F6408Q0C K9F6408U0C PIN CONFIGURATION (WSOP1) N.C N.C DNU N.C N.C N.C R DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 K9F6408U0C-VCB0,FCB0/VIB0,FIB0 ...
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... K9F6408Q0C K9F6408U0C PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
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... K9F6408Q0C K9F6408U0C Figure 1. FUNCTIONAL BLOCK DIAGRAM Command Figure 2. ARRAY ORGANIZATION 16K Pages 1st half Page Register (=1,024 Blocks) (=256 Bytes) I/O 0 1st Cycle A 0 2nd Cycle A 9 3rd Cycle A 17 NOTE : Column Address : Starting Address of the Register. ...
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... K9F6408Q0C K9F6408U0C PRODUCT INTRODUCTION The K9F6408X0C is a 66Mbit(69,206,016 bit) memory organized as 16,384 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans- fer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... Vcc(max) OUT I/O pins Vcc Except I/O pins V - K9F6408Q0C :I =-100 A OH Vcc K9F6408U0C :I =-400 A OH K9F6408Q0C :I =100uA OL K9F6408U0C :I =2.1mA OL K9F6408Q0C :V =0.1V OL K9F6408U0C :V =0.4V OL can overshoot to V +0.4V for durations less FLASH MEMORY Rating K9F6408Q0C(1.8V) K9F6408U0C(3.3V) -0 2.45 -0 4.6 -0 2.45 -0 4.6 -0 2.45 -0 4.6 - 125 ...
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... The 1st block, which is placed on 00h block address, is guaranteed valid block, does not require Error Correction program/erase cycles. AC TEST CONDITION (K9F6408X0C-XCB0:TA K9F6408X0C-XIB0:TA=- K9F6408Q0C: Vcc=1.70V~1.95V , K9F6408U0C: Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times ...
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... REA t RHZ t CHZ REH WHR t RST CRY t 100 CEH 11 FLASH MEMORY K9F6408U0C Min Max ( K9F6408Q0C K9F6408U0C Max Min - 100 - - 5/10/500 (1) - 5/10/500 - 100 - 50 +tr( +tr(R/B) (3) ...
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... K9F6408Q0C K9F6408U0C NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The informa- tion regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F6408Q0C K9F6408U0C NAND Flash Technical Notes Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F6408Q0C K9F6408U0C NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F6408Q0C K9F6408U0C Pointer Operation of K9F6408U0C Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’ 00h’ command sets the pointer to ’ A’ area(0~255byte), ’ 01h’ command sets the pointer to ’ B’ area(256~511byte), and ’ 50h’ command sets the pointer to ’ ...
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... K9F6408Q0C K9F6408U0C System Interface Using CE don’ t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... K9F6408Q0C K9F6408U0C Command Latch Cycle CLE CE WE ALE I Address Latch Cycle CLE CE WE ALE I CLH CLS ALH ALS Command t CLS ALH ALS t ALS ...
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... K9F6408Q0C K9F6408U0C Input Data Latch Cycle CLE CE t ALS ALE WE I Serial access Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 0 DIN 1 (CLE=L, WE=H, ALE=L) ...
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... K9F6408Q0C K9F6408U0C Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE ALE RE A 00h or 01h I Column Address R/B t CLS t CLH WHR 70h On K9F6408U0C_T,Q or K9F6408U0C_V,F CE must be held low during ...
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... K9F6408Q0C K9F6408U0C READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE RE 00h or 01h I Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE 50h I R/B M Address On K9F6408U0C_T,Q or K9F6408U0C_V,F CE must be held low during AR2 Dout N ...
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... K9F6408Q0C K9F6408U0C SEQUENTIAL ROW READ OPERATION (only for K9F6408U0C-T,Q and K9F6408U0C-V,F valid within a block) CLE CE WE ALE RE 00h I R/B M PAGE PROGRAM OPERATION CLE ALE RE I/O ~ 80h Sequential Data Column Input Command Address R/B Dout ...
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... I 90h Read ID Command (ERASE ONE BLOCK DOh 17 22 Busy Erase Command t CLR t AR1 t REA 00h Address. 1cycle K9F6408Q0C K9F6408U0C 22 FLASH MEMORY t BERS 70h I/O 0 Read Status I/O 0 Command Device ECh Code* Maker Code Device Code Device Device Code* 39h E6h ...
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... K9F6408Q0C K9F6408U0C DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis- ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...
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... K9F6408Q0C K9F6408U0C Figure 4. Read2 Operation CLE CE WE ALE R/B RE 50h Start Add.(3Cycle) I Don't Care) Figure 5. Sequential Row Read1 Operation (only for K9F6408U0C-T,Q and K9F6408U0C-V,F valid within a block) R/B I/O ~ Start Add.(3Cycle 00h 01h & ...
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... K9F6408Q0C K9F6408U0C Figure 6. Sequential Row Read2 Operation (GND Input=Fixed Low) (only for K9F6408U0C-T,Q and K9F6408U0C-V,F valid within a block) R/B 50h Start Add.(3Cycle) I Don t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 single page program cycle ...
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... K9F6408Q0C K9F6408U0C BLOCK ERASE The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. ...
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... Figure 10. RESET Operation R/B I FFh Table3. Device Status Operation Mode t CLR t CEA t AR1 tREA 00h Address. 1 cycle K9F6408Q0C K9F6408U0C RST t RST After Power-up Read 1 27 FLASH MEMORY Device ECh Code* Maker code Device code Device Device Code* 39h E6h after the Reset command is written. Reset command is ...
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... K9F6408Q0C K9F6408U0C READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... Data Protection & Powerup sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V/2V(K9F6408Q0C:1.1V, K9F6408U0C:2V). WP pin provides hardware pro- tection and is recommended to be kept at V before internal circuit gets ready for any command sequences as shown in Figure 12. The two step command sequence for program/ erase provides additional software protection ...