EMC326SP16AK Emlsi Inc., EMC326SP16AK Datasheet - Page 14

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EMC326SP16AK

Manufacturer Part Number
EMC326SP16AK
Description
2mx16 Bit Cellularram
Manufacturer
Emlsi Inc.
Datasheet
Figure 8: Refresh Collision During Variable-Latency READ Operation
Note:
Non-default BCR settings for refresh collision during variable-latency READ operation: Latency code 2 (3 clocks); WAIT active LOW; WAIT asserted
during delay.
LB#/UB#
DQ[15:0]
A[20:0]
ADV#
WAIT
WE#
CLK
OE#
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
OH
OL
Additional WAIT states inserted to allow refresh completion
High-Z
Address
Valid
14
D0
D1
EMC326SP16AK
D2
Don’t Care
2Mx16 CellularRAM
D3
Undefined

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