E28F320J5100 Intel, E28F320J5100 Datasheet - Page 47

• Manufacturer Part Number: E28F320J5100
• Manufacturer: Intel

NOTES:
CE
CE
ADDRESSES [A]
X
1
PRELIMINARY
, or CE
low is defined as the first edge of CE
DATA [D/Q]
BYTE# [F]
2
DQ
WE# [W]
that disables the device (see Table 2, Chip Enable Truth Table ).
OE# [G]
RP# [P]
CE
Disabled (V
Enabled (V
0
-DQ
X
V
[E]
CC
15
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
OH
OL
IH
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
IL
)
)
Figure 16. AC Waveform for Read Operations
INTEL
Standby
High Z
0
, CE
®
R5
1
StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT
, or CE
R11
R6
Address Selection
2
Address Stable
that enables the device. CE
Device
R2
R3
R7
R12
Valid Output
R4
R1
Data Valid
R13
X
high is defined at the first edge of CE
R10
R8
R9
R14
High Z
0606_16
0
47
,