MT47H64M16HR-25E AIT:H Micron, MT47H64M16HR-25E AIT:H Datasheet - Page 25

• Manufacturer Part Number: MT47H64M16HR-25E AIT:H
• Description: Ic Ddr2 Sdram 1gbit 84fbga
• Manufacturer: Micron

Table 10: DDR2 I
Notes: 1–7 apply to the entire table
PDF: 09005aef840eff89
1gbddr2_ait_aat.pdf – Rev. C 7/11 EN
Parameter/Condition
Operating burst read current: All banks open,
continuous burst reads, I
(I
t
valid commands; Address bus inputs are switching;
Data bus inputs are switching
Burst refresh current:
command at every
CS# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus
inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤
0.2V; Other control and address bus inputs are
floating; Data bus inputs are floating
Operating bank interleave read
current: All bank interleaving reads, I
= 4, CL = CL (I
=
t
commands; Address bus inputs are stable during de-
selects; Data bus inputs are switching; See on page
for details
RP =
RCD (I
DD
t
CK (I
), AL = 0;
t
RP (I
DD
DD
); CKE is HIGH, CS# is HIGH between valid
),
DD
t
RC =
); CKE is HIGH, CS# is HIGH between
t
DD
CK =
), AL =
t
RC (I
t
t
DD
CK (I
RFC (I
Notes:
DD
Specifications and Conditions (Die Revision H) (Continued)
t
RCD (I
DD
t
OUT
),
CK =
DD
),
t
RRD =
) interval; CKE is HIGH,
t
= 0mA; BL = 4, CL = CL
RAS =
DD
t
1. I
2. V
3. I
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
5. Definitions for I
6. I
7. The following I
CK (I
) - 1 ×
t
UDQS#. I
devices when operated outside of the range 0°C ≤ T
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
When
T
RRD (I
DD
DD
DD1
DD
t
DD
C
RAS MAX (I
≤ ≤ 0°C
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
, I
); REFRESH
OUT
t
= 1.8V ±0.1V, V
CK (I
DD4R
DD
= 0mA; BL
DD
),
DD
, and I
t
I
ed by 2%; and I
RCD =
values must be met with all combinations of EMR bits 10 and 11.
DD2P
);
V
V
Inputs stable at a HIGH or LOW level
Inputs at V
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
DD
t
IN
IN
CK
DD
DD
),
DD7
≤ V
≥ V
and I
values must be derated (I
conditions:
DDQ
IL(AC)max
IH(AC)min
require A12 in EMR to be enabled during testing.
DD3P(SLOW)
Symbol
REF
= 1.8V ±0.1V, V
I
I
I
I
I
DD4R
DD6L
DD5
DD6
DD7
25
= V
DD6
Electrical Specifications – I
DDQ
and I
1Gb: x8, x16 Automotive DDR2 SDRAM
must be derated by 4%; I
/2
DD7
Configuration
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DDL
must be derated by 7%
x8, x16
= 1.8V ±0.1V, V
x16
x16
x16
x8
x8
x8
DD
limits increase) on IT-option and AT-option
C
≤ 85°C:
DD4R
-25E/
REF
-25
120
150
145
150
210
260
7
5
= V
and I
2010 Micron Technology, Inc. All rights reserved.
DDQ
DD5W
/2.
DD
-3E/
110
125
140
145
185
230
-3
7
5
Parameters
must be derat-
C
≤ +85°C.
Units
mA
mA
mA
mA