SST30VR023-500-C-WH Silicon Storage Tech, SST30VR023-500-C-WH Datasheet - Page 9

• Manufacturer Part Number: SST30VR023-500-C-WH
• Manufacturer: Silicon Storage Tech

2 Mbit ROM + 1 Mbit / 2 Mbit / 256 Kbit SRAM ROM/RAM Combo
SST30VR021 / SST30VR022 / SST30VR023
©2003 Silicon Storage Technology, Inc.
FIGURE 8: SRAM W
Notes: 1. A write occurs during the overlap (T WP ) of a low RAMCS# and low WE#. A write begins at the latest transition among
RAMCS#
Data Out
Address
Data In
WE#
2. T CW is measured from the later of RAMCS# going low to the end of write.
3. T AS is measured from the address valid to the beginning of write.
4. T WR is measured from the end of write to the address change.
5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state.
6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state.
7. D OUT is the same phase of the latest written data in this write cycle.
8. D OUT is the read data of new address
9. ROMCS# = V IH
RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high,
T WP is measured from the beginning of write to the end of write.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
RITE
T AS(3)
High-Z
C
YCLE
T
IMING
T WHZ(5)
D
IAGRAM
http://store.iiic.cc/
T WC
9
T AW
T CW(2)
T WP(1)
High-Z (6)
T DW
Data Valid
T OW
T WR(4)
T DH
(7)
1135 F07.0
T OH
S71135-05-000
(8)
Data Sheet
12/03