FM3164-STR Ramtron, FM3164-STR Datasheet - Page 12

• Manufacturer Part Number: FM3164-STR
• Description: case, leaded, supervisor, reflow, soic, supply, process, max, ram, Interface ICs, package, compatible, voltage, memor...
• Manufacturer: Ramtron

Rev. 2.3
Oct. 2006
0Ch
RC
CC
C2P
C1P
0Bh
SNL
WP1-0
VBC
VTP1-0
0Ah
WDE
WDT4-0
Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write.
VTP select. These bits control the reset trip point for the low VDD reset function. Nonvolatile, read/write.
Event Counter Control
Read Counter. Setting this bit to 1 takes a snapshot of the four counters bytes allowing the system to read the
values without missing count events. The RC bit will be automatically cleared.
Counter Cascade. When CC=0, the event counters operate independently according to the edge programmed by
C1P and C2P respectively. When CC=1, the counters are cascaded to create one 32-bit counter. The registers of
Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P is
“don’t care” when CC=1. Battery-backed, read/write.
CNT2 detects falling edges when C2P = 0, rising edges when C2P = 1. C2P is “don’t care” when CC=1. The value
of Event Counter 2 may inadvertently increment if C2P is changed. Battery-backed, read/write.
CNT1 detects falling edges when C1P = 0, rising edges when C1P = 1. The value of Event Counter 1 may
inadvertently increment if C1P is changed. Battery-backed, read/write.
Companion Control
Serial Number Lock. Setting to a 1 makes registers 11h to 18h and SNL permanently read-only. SNL cannot be
cleared once set to 1. Nonvolatile, read/write.
VBAK Charger Control. Setting VBC to 1 causes a 15 µA trickle charge current to be supplied on VBAK.
Clearing VBC to 0 disables the charge current. Nonvolatile, read/write.
Watchdog Control
Watchdog Enable. When WDE=1 the watchdog timer can cause the /RST signal to go active. When WDE = 0 the
timer runs but has no effect on /RST. Note as the timer is free-running, users should restart the timer using WR3-0
prior to setting WDE=1. This assures a full watchdog timeout interval occurs. Nonvolatile, read/write.
Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog
timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR3-0. Nonvolatile, read/write.
WDE
SNL
D7
D7
D7
-
Write protect addresses
None
Bottom 1/4
Bottom 1/2
Full array
VTP
2.6V
2.9V
3.9V
4.4V
Watchdog timeout
Invalid – default 100 ms
100 ms
200 ms
300 ms
2000 ms
2100 ms
2200 ms
2900 ms
3000 ms
Disable counter
.
.
.
.
.
.
D6
D6
D6
-
-
-
VTP1
0
0
1
1
D5
D5
D5
-
-
-
VTP0
WP1
0
1
0
1
0
0
1
1
WDT4 WDT3 WDT2 WDT1 WDT0
WDT4
WP1
D4
D4
D4
0
0
0
0
1
1
1
1
1
1
-
WP0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
WDT3
WP0
D3
RC
D3
D3
0
0
0
0
1
1
1
1
1
1
WDT2
0
0
1
1
0
0
1
0
1
1
VBC
D2
CC
D2
D2
0
1
0
1
0
1
0
1
0
1
WDT1
VTP1
C2P
D1
D1
D1
FM3104/16/64/256
Page 12 of 25
WDT0
VTP0
C1P
D0
D0
D0